操作干擾特性分析於非重疊式離子植入之非揮發性記憶體矩陣

Characterization of Operational Disturbances in the Non-Overlapped Implantation Non-Volatile Memory Array

王敏郎(Min-Lang Wang)

指導教授 ： 鄭湘原

中原大學/工學院/電子工程研究所/碩士(2009年)

https://doi.org/10.6840/cycu200900643

摘要

近年來，為了增加記憶體密度及減少元件的尺寸，利用氮化矽做為電荷存取的記憶體，引起了很大的迴響。新型的非重疊式離子植入之非揮發性記憶體(Non-Overlapped Implantation Non-Volatile Memory，以下簡稱為NOI NVM)，也是目前氮化矽記憶體的應用之一。與其他氮化矽記憶體比較，特別是應用在標準的CMOS邏輯產品中的嵌入式非揮發性記憶體，NOI NVM，是一個無需增加額外光罩和複雜製程的最佳解決方案。
本論文將以此新型NOI NVM矩陣電路的干擾特性做為研究主題，探討8乘8記憶單元矩陣於目標位元寫入和抹除時，非寫入和非抹除位元之干擾現象，進而評估此NOI元件可設計之最大記憶體矩陣面積。經由實驗發現，同一矩陣內非寫入和非抹除位元，將隨著長時間閘極偏壓的作用下而出現被干擾現象，此類干擾現象，將使得NOI元件之氮化矽間隙壁內儲存狀態產生變化，進而改變元件讀取時之通道臨界電壓以致影響電路判別，侷限矩陣電路設計面積。若藉由施予汲極和源極的偏壓，降低氮化矽間隙壁週圍電場，此現象將可獲得改善。

關鍵字

非重疊式離子植入之非揮發性記憶體 ； 干擾特性

並列摘要

In order to achieve better device scalability and higher memory density array, the nitride charge trapping memories have attracted much interest, recently. The novel Non-Overlapped Implantation Non-Volatile Memory (NOI NVM) is also developed for memory applications. Especially for embedded memory applications, the NOI NVM’s fabrication is the simplest solution which is fully compatible with existing foundry logic CMOS technologies and requires no additional mask as well as complex processes.
This work characterizes operational disturbances in the Non-Overlapped Implantation Non-Volatile Memory array. During the array operations, the reverse tunneling behavior is found in unselect cells after high gate voltage and long stress time. As a result, the charge storage status is altered in the nitride spacer. The threshold voltage (Vth) deviation will degrade its performance in readout circuit and therefore limit the memory density. This disturbance can be improved by applying additional bias at unselect cells’ source and drain to reduce the field in the nitride spacer. The results have the positively shown feasibility NOI devices can be used for a high density embedded memory.

並列關鍵字

disturbances ； Non-Overlapped Implantation Non-Volatile Memory

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