非重疊離子佈植記憶體陣列與單一元件之保存能力特性分析與比較

Characterization of Data Retention Capability in NOI NVM array and Single NOI cell

林瑋宸(Wei-Chen Lin)

指導教授 ： 鄭湘原

中原大學/工學院/電子工程研究所/碩士(2014年)

https://doi.org/10.6840/CYCU.2014.00017

摘要

近年來隨著通訊的蓬勃發展與可攜式相關產品日益的增長，對非揮發性記憶體的需求與重要性也日益提高，由於可攜式產品暢銷與攜帶便利之因素，所需之零組件需持續縮小，且功率消耗或速度等相關性能必須提升，以維持品質的順暢度來滿足消費者的需求。
本篇論文主要是探討單一非重疊離子佈植非揮發性記憶元件(Non Overlapped Implantation NVM)與1M bits NOR型非重疊離子佈植記憶元件陣列進行資料保存度實驗之後的臨限電壓分佈關係，並分析其單一元件與記憶元件陣列之臨限電壓分佈，說明其記憶元件陣列電路之寫入與讀取是呈現非線性的因素，而使得在相同條件下之操作會有不同的閥值電壓現象產生。若是陣列中元件的變異過大造成寫入時的臨限電壓差異增加，則會使分佈加寬，此一現象對於非揮發性記憶體並沒有幫助，且會使得讀取窗口縮小，本篇論文將以單一元件驗證該現象發生之原因，並探討其與資料保存度之關係。

關鍵字

非揮發性記憶體 ； 儲存電荷 ； 資料保存 ； 臨限電壓

並列摘要

In recent years, the rapid development of communications-related products and growth of portable productions increase the demand on non-volatile memory devices. In order to the meet the density and portability of portable productions, the feature size of non-volatile memory devices needs to shrink continuously. Moreover, the relevant performance index such as power consumption and speed must be also improved.
We have investigated the data retention correlation between the non-overlapped implantation non-volatile memory (NOI NVM) and 1M bits NOI NOR-type array in terms of their threshold voltage distribution before and after baking. We characterized their Vth distribution in the single device and NOI array under the same operating conditions. The Vth distribution broadens in the array during the baking test. This effect will decrease the read out window in the NOI array and results in low product yield. In this study, we have verified the consistency and characteristics of Vth in a single NOI device and its array under high temperature stress.

並列關鍵字

threshold voltage ； storage charge ； NVM ； data retention

參考文獻

[1-2] H. Lee, S. Chang, J. Lee and H. Shin, “Characteristics of MOSFET with Non-overlapped Source-drain to Gate,” IEICE Trans. Electron, Vol. E85-C, No. 5, pp. 1079-1085, 2002.

[1-3] Chen, Yuan-Feng, et al. “Characteristics of n-channel MOSFETs with tailored source/drain extension for mask ROM and EEPROM applications,” IEEE transactions on electron devices 56.9 (2009): 2099-2106.

[1-4] Eitan, Boaz, et al. “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” Electron Device Letters, IEEE 21.11 (2000): 543-545.

[2-1] Eitan, Boaz, et al. “NROM: A novel localized trapping, 2-bit nonvolatile Memory cell,” Electron Device Letters, IEEE 21.11 (2000): 543-545.

[2-2] Dipert, Brian, and Lou Hebert. “Flash memory goes mainstream,” Spectrum, IEEE 30.10(1993): 48-52.