針對鰭式場效電晶體電路內跨邏輯閘錯誤之錯誤模擬器以及測試向量產生器

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

江冠穎(Kuan-Ying Chiang)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.10255

摘要

在先進製程中，鰭式場效電晶體已經成為最有效解決短通道效應的解決方案。然而，先前的研究顯示，在鰭式場效電晶體中，有些缺陷會造成額外的微小延遲，而這些缺陷無法輕易的被傳統測試圖騰偵測到。有時候，因為製程特性，鰭式場效電晶體電路中的缺陷會同時影響多個邏輯閘，我們稱之為跨邏輯閘缺陷。藉由累計電路上的額外延遲，能夠提升偵測到缺陷的機率。在此論文中，我們針對鰭式場效電晶體內部之跨邏輯閘缺陷，提出FAST錯誤模擬。此錯誤模擬是特別針對鰭斷路跨邏輯閘缺陷所設計。為了產出針對FAST錯誤模擬之測試向量，我們提出FAST測試向量產生器、錯誤模擬器以及測試向量選擇器。實驗結果顯示，我們的測試向量與商業用一次偵測測試向量比較，我們的測試圖騰在FAST涵蓋率上好29%，在FAST SDQL上好4%。

關鍵字

鰭式場效電晶體 ； 微小延遲缺陷 ； 測試向量產生器 ； 錯誤模擬

並列摘要

FinFET has become the most popular solution to overcome short channel effects in advanced technology. However, some research show that defect in FinFET causes extra small delay and the defect is difficult to detect by traditional test sets. Sometimes, defect in FinFET circuits may affect multiple gates due to fabrication process. We named it a cross-gate defect. By accumulating the extra delay induced by the cross-gate defect, we can detect the small delay defect more easily. In this thesis, we proposed a FAST fault model for small delay faults induced by cross-gate defects in FinFET circuits. This fault model is especially designed for fins open cross-gate defect. FAST ATPG, fault simulation, and test pattern selection are also presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL than those of commercial tool timing-unaware 1-detect pattern sets.

並列關鍵字

FinFET ； SDD ； ATPG ； fault simulation

參考文獻

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