電子束曝光是一種使用電子束在晶圓表面上製造圖樣的方式,是光刻技術的延伸應用,電子束曝光的精度可以達到次10奈米量級,因此是一個非常具有潛力的曝光方式,在半導體工業中被廣泛使用於研究下一代超大型積體電路之曝光製造。然而電子束曝光最大的競爭弱勢就是產能的速度相對於193nm之製程太慢,無法提供目前半導體廠大量且快速生產的需求。 可變式形狀電子束技術利用可變的矩形實現所需的曝光圖案,目前超大型積體電路設計在等同面積下電晶體數量越來越多,且電路設計越來越複雜,可變式形狀電子束技術得需要大量的曝光次數,導致產率不良。單元投影式電子束由於一次曝光即可製作較大的圖案,故產能可大大提升。 因此,在這篇論文中,我們將提出單元投影式電子束的方法,包括電路布局圖的正規化、單元設計以及電路布局圖的投影演算法。我們主要致力於產能的提升。 最後,實驗數據顯示出我們的演算法在最重要的產能部份,優於先前所發表的演算法2.1倍以上,另外我們定了更多的限制維持住原本的電路功能。
In recent decades, electron-beam lithography (EBL) is one of the strong candidates to draw custom shapes on the surface of wafer covered with electron-sensitive film called resist. The primary advantage of EBL is that it can draw custom patterns in sub-10nm resolution since the electron beam can change the solubility of the resist. Nevertheless, the low throughput of EBL is limiting its capability to mass production. Variable Shaped Beam (VSB), one of the EBL technologies, exploits a set of variant rectangles to construct the layout. As the VLSI circuit design getting larger and more complicated, it takes more numbers of shots of VSB to realize modern design layouts. Thus, the bottleneck which limits the application of EBL system is the manufacturing feasibility. One approach to improve the throughput of VSB is the Character Projection (CP) techniques which constructs the layout with pre-designed characters for reducing the number of shots. In this thesis, we will introduce a series of methods, including character design, layout normalization and layout matching for improving the throughput of Character Projection (CP) Electron-Beam Lithography. According to the experimental results, our throughput is 2.1 times faster than the previously published algorithm. Besides, we set more conditions to ensure the circuit function unchanged.