快速熱製程及切割對矽金氧半元件特性之影響

隨著電子電路設計與半導體製程技術的飛快進步，在半導體元件製程中的每一個小細節都變成相當重要，關係著元件的電特性是否良好。特別是閘極介電層的品質能決定ULSI電路的穩定度與電特性表現。我們將會集中以快速熱製程如何影響介電層電特性。起先，我們觀察到有不同厚度的MOS (P) 元件表現出不同的電流曲線，似乎意味著在電特性與介電層生長的方式可能存在某種特定關係。本篇論文，我們設計一系列的實驗去觀察氧化層製程如何影響電特性，並發現其中的確存在著規律性。在第二章，我們設計一套實驗，只改變它們的氧化溫度。於是得到了不同閘極介電層的MOS (P)元件，並量測電流和電容曲線去比較它們的電特性。為了突顯其中的規律性，我們提出一個特別的分析方法，即利用MOS (P)結構的漏電流和飽和電流的電流機制來解釋我們看到的現象。在第三章，我們把氧化溫度的條件換成氧化的壓力來作相同的分析。發現其電流曲線也有規律性存在，而我們歸咎其主因為氧化時的壓力，最後並作了TDDB 的量測來驗證我們的假設。在第四章，我們研究了外加施力對MOS (P) 元件的效應。延用之前的同樣製程，並施以外力把晶圓切成兩半。對於切半前後，我們在晶圓上水平和垂直方向量了超過兩百條電流和電容曲線，最後藉由分析電流和電容曲線，我們得到切半行為對於晶圓上元件的等效效應。關於這篇論文，仍然有些相關題目可以去進一步的研究，而我們把這些列在第五章。

關鍵字

氧化層；金氧半元件

並列摘要

With the ultra fast advancement of IC design and semiconductor fabrication technology，every tiny detail in the process of semiconductor devices has become a key point to determine whether the electrical performance can be good or not. Especially, the quality of gate dielectric layer determines the reliability and electrical performance of ultra large scale integrated (ULSI) circuit. We focus on how the processes in repaid thermal processor (RTP) affect the electrical characteristics quality of gate dielectric layer. To start with, we observed the differences of the J-V curves of MOS (P) devices with different gate dielectric thicknesses. It seemed that there must be some relationship between the electrical performance and the way in which the gate dielectric layer was grown. In this thesis, we set up series of experiments to watch how the oxidation process affects the electrical characteristics and truly found some regularity between them. In chapter 2, we set up a series of experiments, which were all the same except for the oxidation temperature. Thus, MOS (P) devices of different gate dielectric thicknesses were obtained and measurements of J-V and C-V curve were made to compare their electrical characteristics. A special analysis method was used here to strengthen the regularity. The two current mechanisms of the leakage current and the saturation current of MOS (P) structures were proposed to explain our observation. In chapter 3, we replace the oxidation temperature factor with the oxidation pressure factor to do the same analysis. Another regularity between the J-V curves and oxidation pressures was found and we blamed the oxidation pressures for the major problem. Finally, TDDB measurements were made to support our supposition. In chapter 4, we studied the effects of external forces on MOS (P) devices. We continue the same fabrications and applied external force to deform the sample severely, scribing it into two halves. Over two hundred J-V and C-V measurements were made vertically and horizontally before and after cutting. Finally, we also concluded an equivalent effect of the scribing action by analyzing these J-V and C-V measurements. Finally, some other works around this thesis that remain to be done have been listed in chapter 5.

並列關鍵字

MOS ； Oxide

參考文獻

[1] H.E Maes, s.h. smani, and G.L. Heyns, ”Effect of a high temperature hydrogen anneal of the memory retention of metal-nitride-oxide-silicon transistors at elevated temperature”, J. Appl. Phys., Vol.52 no. 6 pp.4348-4350, 1981.

[2] Y. Husia and K.L. Ngai, “MNOS traps distribution gate dielectrics MNOS”, Japan J. Appl. Phys., Vol. 19, pp.245-248, 1980.

[3] L. M. Landsberger and q. A. tiller, “ two-steps oxidation experiments to determine structural and thermal history effects in thermally grown SiO2 films on silicon ” Journal of Electrochem. Soc., Vol. 137, pp.2825, 1990.

[4] K. C. Lee and J. G. Hwu, “17.3% Efficiency Metal-Oxide-semicondctor (MOS) Solar Cells with Liquid-Phase-Deposited Silicon Dioxide”. Ieee Electrojn device Letters, Vol. 18, No. 11, pp. 565-567, 1967.

[6] M. J. Jeng and J. G. Hwu, “Enhanced nitrogen incorporation and improved breakdown endurance in nitride3d gate oxides prepared by anodic oxidation followed by rapid thermal nitridation in N2O,” Applied. Physics Letters, Vol.69, No.25, pp. 3875-3877, 1996.

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快速熱製程及切割對矽金氧半元件特性之影響

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