適用於晶片內網路系統之可靠低延遲非同步傳輸技術

在未來的SoC時代中,晶片內傳輸(On-Chip Communication)機制是一個相當重要的討論議題，有別於傳統上使用的匯流排(On-Chip Bus)架構，我們做的是一個晶片內網路(On-Chip Network)的架構,主要解決傳統的匯流排(Bus)所遭遇到的困難，例如:連線複雜度、串線干擾 (cross-talk)、資料同步化、提供多重時脈來源、延展性、傳輸頻寬等的問題。針對提供多重時脈來源(multiple clock domains)這項議題，傳統的晶片系統都是單一時脈來源，當晶片內矽智財(IP)數量增加到一定數目時，整個系統的效能勢必會下降，而當晶片內系統是由多個時脈供應時，各個不同時脈間的矽智財要互傳資料時，傳送資料的可靠性(Reliability)就非常重要，而非同步傳輸技術可以達到這一項要求，在各種非同步傳輸技術中，全區域性非同步區域性同步(Globally Asynchronous Locally Synchronous)技術是我們所需要的，GALS具有在不同的時脈相位和不同的時脈頻率下，讓資料可以正常的傳收，然而傳統的GALS技術所造成的問題，包括傳送資料時所造成的高延遲時間、低資料產能、高能量消耗，對此，我們提出一種新的非同步傳輸機制，本設計為一個具可靠性和低延遲特性的資料傳輸機制，讓資料可以在不同的時脈來源下作有效的傳送與接收，主要利用非同步傳輸協定的交握(handshake)特性，在不同時脈相位(clock phase)和時脈頻率(clock frequency)下，資料可以可靠地被傳輸。有別於傳統的非同步傳輸機制所造成高延遲的限制，我們做的是具有低延遲特性的非同步傳輸機制，除了讓資料可以在最少的時間內傳送之外，並間接達到最高的資料產能和較低的消耗能量，我們的架構相較於傳統的非同步傳輸機制，在傳送端和接收端各有特殊的機制，在傳送端有個流量控制的機制，在接收端則有一個時脈相位調整的機制，傳送端的流量控制機制主要控制傳輸資料的頻寬，而接收端的相位調變機制主要適用在高頻狀況下，它的功用為補償時脈相位誤差。根據模擬的結果，我們提出的非同步傳輸技術可以在不同的時脈來源下讓資料可靠地作傳送，我們的架構相較於傳統的GALS技術確實具有較低的時間延遲，較高的資料產能和較低的消耗能量三項特性，在延遲(latency)部分，可以節省50%到83%的延遲時間，在資料產能(throughput)部分，可以提升成原本的2倍到6倍，在能量(energy)部分，可以節省40%到82%能量消耗。最後，我們實作一個基本的晶片內網路架構的平台，這個網路平台是一個3×3網狀架構，我們提出的非同步傳輸技術在這個系統平台中扮演著資料傳輸的角色，並測試多點傳送多點接收(Multiple Input Multiple Output)與多點傳送單點接收(Multiple Input Single Output)兩種狀況，模擬結果顯示出預期的可靠性與低延遲特性的結果，並以TSMC 0.18um 1P6M製程去實現我們提出的非同步傳輸技術，電路方面，總共面積為920×920um2，最高操作頻率為500MHz，消耗的功率為8mW。

關鍵字

晶片內網路；非同步傳輸技術；全區域性非同步區域性同步

並列摘要

In future SoC designs, on-chip-communication (OCC) is a very important issue, unlike traditional on-chip bus architecture, and we adopt on-chip network architecture to solve the problems caused by on-chip bus architecture, for example: wire complexity, crosstalk, data synchronization, can not support multiple clock domain, scalability, etc. Focusing on the issue of supporting multiple clock domains, conventional SoC is supported by a single clock source and the total system performance will degrade when the numbers of IP on a system becomes larger. Thus, we adopt multiple clock sources; the reliable transmission method between multiple clock domains is asynchronous transmission technique. In several asynchronous transmission technologies, globally asynchronous locally synchronous (GALS) is a technique which can achieve transmitting data between different clock phase and different clock rate. In the same way, our research focus on transmitting data reliably between different clock domains, however, it improves the limitation of GALS technique. Compared with conventional asynchronous transmission technique, our proposed asynchronous transmission technique has the characteristics of low latency, high data throughput and low latency. Unlike conventional asynchronous transmission technique, our transmitter has a flow control mechanism and receiver has an adaptive phase mechanism, the flow control mechanism is to control the transmission bandwidth and the adaptive phase mechanism is suitable for high clock rate, its function is to compensate the clock phase error. Based on the simulation results, our proposed asynchronous transmission technique can transfer data reliably between separate clock domains. Making a comparison with conventional GALS technique, our proposed asynchronous technique saves 50%~83% latency timing, improves 2x~6x data throughput and saves 40%~82% energy consumption. We implement a basic OCN system platform, the platform is a 3×3 mesh topology and we integrate our proposed asynchronous technique into this platform, the simulation result shows the reliability and low latency that we expect. Finally, implementation on TSMC 0.18um 1P6M technology, the circuit area is 920×920um2, the maximum operation rate is 500MHz, and power consumption is 8mW.

並列關鍵字

On-Chip Network ； Asynchronous transmission technique ； GALS

參考文獻

[1] R. Ho, K. Mai, and M. Horowitz, “The Future of Wires,” Proc. IEEE, Apr. 2001, pp. 490-504.

[4] “International Technology Roadmap for Semiconductors.” http://public.itrs.net/.

[5] L. Benini and G. De Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1, pages 70-78, 2002.

[8] J. N. Seizovic, “Pipeline synchronization,” in Proc. Of ASYNC’94, pp. 87–96, 1994.

[11] K. Y. Yun and A. E. Dooply, “Pausible clocking based heterogeneous systems,” in IEEE Trans. on VLSI systems,pp. Vol.7, no.4:482–487, Dec. 1996.

國際替代計量

適用於晶片內網路系統之可靠低延遲非同步傳輸技術

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