應用於晶片網路之緩衝器時脈閘控架構設計

Design of Buffer Clock-Gating Architecture for Network-on-Chip

黃啟翰(Chi-Han Huang)

指導教授 ： 李宗演

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2011年)

摘要

由於多核心晶片的世代已經來臨，為了滿足多核心通訊的傳輸率，因此近幾年晶片網路(NoC)一直被視為解決多核心傳輸的問題。雖然高傳輸率被解決，但卻衍生出功率消耗、面積與死結等等問題。本論文提出時脈閘控架構設計來改善晶片網路的功率消耗與面積。當slot狀態處於Full(滿)或Empty(空)時，本方法對buffer進行clock-gating以減少功率消耗。根據實驗結果，當資料封包長度為10 bits時，本架構比IntelliBuffer架構的功率消耗可降低16.8%，面積減少45.9%以及時脈延遲減少2.7%。而與文獻[3]比較則功率消耗減少38%以及面積減少15.2%。當資料封包長度為18 bits時，本架構比IntelliBuffer架構的功率消耗可降低22.4%，面積減少40.9%以及時脈延遲減少2%。而與文獻[3]比較則功率消耗減少32.9%，面積減少13%以及時脈延遲減少2%。

關鍵字

晶片網路 ； 繞線路徑演算法 ； 路由器 ； 時脈閘控 ； Full Clock-Gating ； IntelliBuffer

並列摘要

The multicore system is more popular architecture in recently. The NoC (Network-on-Chip) architecture is proposed to solve the problem of high performance and throughput in a multicore system but it derived some problems such as of power consumption, area and deadlock, etc. This paper proposes a buffer clock-gating (BCG) architecture to improve the power consumption and area of buffers in Network-on-Chip. When buffer content is full or empty, the BCG uses clock-gating technology to gating buffer period to reduce power consumption. When data packet length is 10 bits: comparison with IntelliBuffer [2], the proposed method reduced 16.8% on power consumption, 45.9% on area and 2.7% on time delay and comparison with [3], the proposed method reduced 38% on power consumption and 15.2% on area. When data packet length is 18 bits: comparison with IntelliBuffer [2], the proposed method reduced 22.4% on power consumption, 40.9% on area and 2% on time delay and comparison with [3], the proposed method reduced 32.9% on power consumption, 13% on area and 2% on time delay.

並列關鍵字

NoC ； Routing Algorithm ； Router ； Clock-Gating ； Full Clock-Gating ； IntelliBuffer

參考文獻

[1] L. Benini and G. De Micheli, “Network on chips: a new SoC paradigm,” IEEE computer, vol. 35, no. 1, pp. 70-78, Jan, 2002.

[2] C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das and M. Irwin, “On the Effects of Process Variation in Network-on-Chip Architectures,” IEEE Transactions on Dependable and Secure Computing, vol 7, Issue 3, July-Sept, 2010, pp. 240-254.

[4] M. el ghany, M.A. El-Moursy and M. Ismail, “High throughput high performance NoC switch,” in Proceeding of 2008 NORCHIP, pp. 237 – 240, 16-17 Nov, 2008.

[9] A. Agarwal, C. Iskander and R. Shankar, “Survey of network on chip (NoC) architectures and contributions,” Journal of Engineering, Computing and Architecture, vol 3, no. 1, 2009.

[13] R. Bondade and M. Dongsheng “Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips” IEEE Transactions on Circuits and Systems, vol 57, Issue 11, Nov, 2010, pp. 2890-2903.