應用於晶片網路之低功率網路介面設計

Design of a Low Power Network Interface for Network-on-Chip

黃政德(Cheng-De Huang)

指導教授 ： 李宗演

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2012年)

摘要

近年來多核心運算架構常使用於晶片系統(System-on-Chip, SoC)中。由於晶片系統中包含多個處理單元(Processing Elements, PEs)以及相對應的互連結構，各處理單元之間訊息交換相當頻繁導致功率消耗與資料延遲問題，因此有許多研究提出晶片網路(Network-on-Chip, NoC)的方法，使得低功率高效能的設計也變成了重要的議題。若能移除在序向電路(Sequential Circuit)中不必要的切換動作(Switching Activity)，將能大幅度減少功率消耗。在本篇論文提出應用於晶片網路之網路介面時脈閘控架構設計來改善網路介面中緩衝器的功率損耗。因傳送大量資料導致FIFO在Full與Empty狀態下等待讀取時間不短，若能使緩衝器進入休眠(Shut Down)狀態，並且改善其有限狀態機(Finite State Machine)的狀態策略，而利用時脈閘控技術將不必要時脈去掉，則可有效降低緩衝器功率消耗。由實驗結果得知，本文所提出的網路介面之時脈閘控架構中增加少許硬體資源，最大可降低30%功率消耗。

關鍵字

晶片網路 ； 網路介面 ； 時脈閘控 ； 功率消耗

並列摘要

In recent years, multi-core computing architectures have been used in System-on-Chip (SoC), which contains multiple processing elements and corresponding, interconnects structure. Messages are switched among the processing elements quite frequently. Therefore, the data latency and power consumption issues are generated. Many studies have proposed to solve those issues in a Network-on-Chips (NoC). If the function unit to remove unnecessary switching activity, it dramatically reduce power consumption degree. This work proposes Clock Gating Circuit (CGC) architecture to reduce the power consumption in Network-on-chip. When buffer state is full or empty, the proposal circuit will gate buffer period to reduce power consumption. The experimental results show that the proposed Clock-Gating technique can maximum reduces 30% power consumption under increasing a few hardware resources.

並列關鍵字

NoC ； Network Interface ； Clock Gating ； Power Consumption

參考文獻

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