以應用導向之晶片網路設計及其模擬機制

Application-Driven Design and Evaluation of Network-on-Chip for Many-Core Systems

黃世傑(Shih-Chieh Huang)

指導教授 ： 金仲達

國立清華大學/電機資訊學院/資訊工程學系/博士(2013年)

摘要

晶片網路已經成為多核心系統主要的連結架構，故對於晶片網路更深入的瞭解與探索其特性在近期的研究已成為一個重要的主題。在此論文中，我們以應用程式的角度切入，深入瞭解多核心應用程式之特性，探討這些特性與晶片網路之間的關係。利用應用程式之規律行為的特性（如迴圈，空間與時間的重複存取特性），設計出所對應之適合的晶片網路。此論文之主要貢獻為：1. 利用應用程式之特性，我們可以幫助晶片網路做更好的省電機制 2. 利用應用程式特性，設計出可以快速評估晶片網路效能之模擬機制。相較於過去的方法，我們的實驗證明以應用程式的角度切入，可以帶來比單純以硬體角度切入更好的效能。

關鍵字

晶片網路 ； 多核心 ； 模擬

並列摘要

As the number of cores in a chip increases continuously, Network-on-Chip (NoC) becomes the primary choice for interconnecting the nodes, so exploring the design of NoC is hence important for fully utilizing the power of the nodes. Unfortunately, when designing the interconnect fabric, the implications coming from the applications running on top of the NoC are usually ignored and wasted. Instead, they mostly rely on fixed parameters decided in very early-design stage. Even if dynamic adaptations at runtime are designed, they rely only on simple counters available in the hardware. Therefore, the NoC design is usually conservative and even does not fit the target applications in the end.

In fact, the information coming from the application can dramatically improve the design of NoC. In this thesis, we named this perspective as emph{application-driven NoC design}. Based on the idea of application-driven design, two important topics in the design of NoC are well-researched and solved from the proposed perspective in this thesis. First, we exploited the traffic patterns of the applications running on top of the on-chip networks for saving the power consumption of on-chip network. In previous works, one promising solution is to dynamically adjust the working frequencies/voltages (DVFS) of the switches as well as the links between switches in the NoC to match the traffic flows. The question is when to adjust and by how much. Based on the idea of application-driven design, we propose a hardware mechanism to proactively adjust the frequencies/voltages of switches and/or links in NoC by predicting the application runtime traffic. Different from the previous approaches, our novel approach predicts the traffic from the implicit program behaviors in the network, i.e., loop, repeitive transmissions, which make the DVFS strategy more proactive and accurate. Following up the idea of application-driven design, we proposed a causality-aware simulation methodology for more accurate evaluation. By observing the application behaviors, the causalities between each pair of the nodes in the system can be extracted and embedded into the trace logs, and therefore the accuracy of simulation can be largely improved compared with the conventional trace-driven simulation. Moreover, we further take advantages of the causalities to compress the huge trace logs and design a corresponding traffic generator, named as Attackboard. In Attackboard, it reflects the interactions between each pair of processor and router recorded as several causality-aware small tables, and then it dynamically generates traffic injections to NoC on-the-fly to simulate the real application behaviors at runtime, whereas the traffic is similar to that generated by the original trace but with much lower space overhead.

參考文獻

[1] “Arteris.” [Online]. Available: http://www.arteris.com/

[2] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif,

- processor: A 64-core soc with mesh interconnect,” in Proceedings of International

M. Frank, S. Amarasinghe, and A. Agarwal, “The raw microprocessor: a computational

T. Mohsenin, and B. Baas, “Asap: An asynchronous array of simple processors,” IEEE