具應用感知功能之晶片內網路系統設計

Application-Aware On-Chip Networking System Design for SoC Applications

連育廣(Yu-kuang Lien)

指導教授 ： 吳安宇

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.10410

摘要

隨著晶片系統複雜度增加，直接連線實現將越益困難。而現今常用的匯流排也會遭遇延展性與傳輸延遲的限制，使得系統的效能降低、負荷遽增。
OCN（On-Chip Networking），主要是透過晶片內網路架構及系統的規劃，建構一個高效能、可信賴的晶片通訊環境，以減少連線的複雜度，並解決晶片系統中匯流排架構的延展性問題。
本論文中，我們針對SoC晶片實現提出一套OCN系統設計流程及方法（AMAP），根據所設計之多種類晶片網路基本元件，在符合SoC應用需求下，我們提出二項式收斂圖映法（Binomial Mapping Method），用以建構出較為經濟之網路拓樸，在頻寬上可節省37%，傳輸延遲可節省46%；依照其需求曲線，進一步最佳化整體效能與硬體成本（Low Cost Optimization）。此外我們提出動態最適調節機制，讓OCN在動態運作中可根據系統整體需求及實際資料，有效提升交換引擎之使用率，進而節省硬體需求，總體硬體成本節省可達到75~87.5%。
在傳輸基礎架構建立後，我們結合CoWare ConvergenSC進行網路拓樸參數之調整與軟硬體共同模擬，藉此評估整體晶片系統實際傳輸之效能表現，決定最適當之晶片網路架構，最後在FPGA上使用實際影像串流（Video Streaming）驗證系統。
我們所提出之OCN系統設計流程及方法很適合實際的SoC應用。特別在未來整合性的SoC環境中，可快速得知系統之效能，在設計初期更有效評估及掌控精確的設計。

關鍵字

晶片 ； 網路 ； 晶片內網路 ； 網路晶片 ； 應用 ； 圖映

並列摘要

As the complexity of SoC systems is increasing, it is hard to interconnect a variety of IPs. OCN (On-Chip Networking) system is a new method to solve the chip communication problems. Based upon pre-defined components and architecture, we can build a high performance and reliable communication environment. Currently, OCN system adopts simple or fixed architectures, such as star and mesh. However, these architectures may cause inefficient bandwidth usage and high hardware cost. Therefore, analytical decision and performance evaluation for OCN system are important issues before implementation.
The goal of this thesis is to map SoC to OCN and optimize the hardware cost. We propose an application-aware design flow and approaches, called AMAP. Due to the differences between SoC Applications, we analyze the requirements of SoC applications. In view of that deciding the location of each IP on OCN system is very important, we propose binomial mapping algorithm to get a fast and efficient 2D-mesh topology. According to the traffic load after mapping, we propose several approaches to optimize the hardware cost and improve the OCN utilization. By using the proposed binomial mapping algorithm, we can save 37% traffic load and 46% Hop. Moreover, we can save 75~87.5% hardware cost by the optimization approaches under bandwidth constraints. Furthermore, the OCN architecture is successfully verified on established infrastructure, CoWare ConvergenSC and FPGA platform.

並列關鍵字

OCN ； NoC ； On-Chip-Network ； Network-on-Chip ； SoC ； Application ； Mapping

參考文獻

[1] ITRS, International Technology Roadmap for Semiconductors, http://public.itrs.net.

[5] L. Benini, G. De Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.

[6] P. Magarshack, P. G. Paulin, “System-on-Chip beyond the Nanometer Wall,” Proceedings of Design Automation Conference (DAC), pp. 419-424, June. 2003.

[8] P. Guerrier, A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 250-256, March. 2000.

[9] K. Goossens, J. Dielissen, A. Radulescu, “AEthereal Network on Chip: Concepts, Architectures, and Implementations,” IEEE Design and Test of Computers, vol. 22, no. 5, pp. 414-421, Oct. 2005.