應用於晶片網路之可調式指令編解碼架構設計

Design of Adaptive Instruction Codec Architecture for Network-on-Chip

陳振軒(Jhen-Syuan Chen)

指導教授 ： 李宗演

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2014年)

摘要

由於多核心系統晶片(System-on-Chip，SoC)在最近幾年相當盛行，且SoC包含多個處理單元(Processing Elements，PEs)，各處理單元之間的訊息交換相當頻繁，若使用傳統Bus架構將無法滿足高傳輸量，因此晶片網路(Network-on-Chip，NoC)被用來解決這種多核心架構通訊所產生的問題，然而低功耗高傳輸架構設計在整個系統上是非常重要的，且NoC傳輸著大量的指令與資料，其中指令碼的相似性與重複性極高，所以本文提出可調式指令編解碼架構(Adaptive Instruction Codec Architecture，AICA)來提高NoC吞吐量(throughput)。使用AICA方法，透過減少指令傳輸封包冗餘性來編碼，使傳輸通道可以有更多空間容納編碼後的資料，進而提高頻寬的使用率以及Router吞吐量，另一方面，因編碼後的封包使Router的傳輸封包次數變少，進而降低NoC在傳輸上的功率消耗。根據實驗結果，與相關研究比較下平均可提升23.5%的吞吐量，降低30.3%的功率消耗。

關鍵字

晶片網路 ； 可調式指令編解碼 ； 吞吐量 ； 冗餘性

並列摘要

The multicore system-on-chip (SoC) rapid development in recently. Messages exchanging between Processing Elements (PEs) are quite frequently. When using the traditional bus architecture cannot be requirement of the high performance. The Network-on-Chip (NoC) architecture was proposed to solve problems with multi-core architecture communication but it derived some problems, such as throughput, power consumption, deadlock and area. In this thesis, an Adaptive Instruction Codec Architecture (AICA) is proposed to improve the throughput and reduce the power consumption of network interface in network-on-chip. NoC transmission large amounts of data and instructions in which have high repeatability and similarity. The proposed AICA architecture decrease packet transmission by reducing the redundancy of instruction. The transmission channel can accommodate more encoded packets, so that the router improves bandwidth utilization and throughput. On the other hand, the encoded packet can reduce power consumption by reducing router transmission times, then the power consumption in network interface will be reduced. The experimental results show that the proposed AICA method can improve 23.5% on throughput and reduce 30.3% on power consumption.

並列關鍵字

NoC ； Adaptive Instruction Codec Architecture ； throughput ； redundancy

參考文獻

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