覆晶封裝中銲料組成對兩界面反應之影響

銲料的微結構與界面介金屬的生成與成長對於電子封裝的可靠度的是很重要的一環。故本研究中分為兩大部分，第一我們使用共晶錫鉛銲料與高鉛95Pb5Sn凸塊進行銲接反應，並針對凸塊界面與基板界面的界面反應進行詳細的研究。此部分的研究中改變三種實驗條件來分析複合銲點(composite solder)的微結構，1.將覆晶銲點經過1-10次迴銲，並同時在迴銲時利用SMT-scope觀察複合銲點的外觀變化，2.將覆晶銲點置於100、130、150、175℃的高溫爐中，經過4000小時的熱處理(high temperature storage)，3.最後將封裝後的覆晶銲點經過溫度循環測試(temperature cycling test)，並觀察其銲點微結構的變化。研究中發現在經過迴銲過後在不同位置的銲點具有不同的外型，此外複合銲點在經過5次迴銲後，在Ni UBM與高鉛凸塊之間發生dewetting的現象而導致裂縫的生成，並隨著回銲次數的增加deweetting 的深度持續往銲奌內延伸，這現象會導致晶片的失效。經過高溫熱處理後，發現晶片端Ni UBM生成的界金屬為(Ni,Cu)3Sn4，這和共晶錫鉛與無鉛銲料的結果有所不同，並且發現複合銲點中Ni的消耗速率較共晶錫鉛快，但是Cu的消耗速率卻比共晶錫鉛來的慢，另外175 ℃下100小時的熱處理後，於Cu墊層和Cu3Sn介金屬之間觀察到有許多微小洞的生成，這些現象皆可能會導致晶片可靠度的下降，有趣的是當時間拉長到3000小時銲點中的Sn相即被消耗完，並且導致界面介金屬Cu6Sn5厚度變薄，研究中並得知界面Cu6Sn5、Cu3Sn和Ni3Sn4介金屬生成活化能分別為116, 67 和88 kJ/mol。在溫度循測試中，由於矽晶片和高分子基版之間的熱膨脹係數(CTE)的差異極大，造成在高低溫循環中，銲點會受到連續循環的疲勞應力，尤其越靠晶片邊緣的銲點其受到的應力更加嚴重，隨著溫度循環測試次數的增加，有趣的是觀察到由於受到與基版平行的橫向剪切應力與溫度影響，而使得銲點中Sn晶粒的粗化以及富Sn相與富Pb相分布呈現水平瘦長的形狀，並隨循環次數增加而更加明顯。另外由in-situ的實驗中發現晶片兩側的銲點的應力方向為沿晶片往基版端45度角，而位在中心點的銲點的受力則與基板端呈水平分布因而導致裂縫的生成，隨著裂縫的成長導致接合部位斷裂，而使銲點阻抗增加甚至短路進而導致此晶片的失效。第二部份的實驗中，使用電鍍的方式製造Ni/Pb5Sn/Cu的擴散偶，並將試片放入150, 175, 200, 250 ℃高溫爐中進行2000小時的反應，實驗發現即使試片沒有經過液態反應，仍會發生spalling現象，實驗結果觀察到反應後Cu端第一生成相為Cu3Sn，並在Cu3Sn上會有micro-voids的生成並隨時間開始聚集，最後導致spalling現象的發生。另外此spalling現象與反應的溫度與銲料的體積有關。Spalling現象發生的驅動力主要是由於熱力學上界面穩定態的轉變。

關鍵字

覆晶封裝；複合銲點；高鉛銲料；溫度循環測試；大規模剝離

並列摘要

This study investigated the intermixing of 95Pb5Sn solder bumps and 37Pb63Sn pre-solder in flip-chip solder joints. In this thesis, we use three experiments to investigate the composites solder. First, the reaction conditions included multiple reflows (up to 10) at 240℃, whereby previously solder-coated parts are joined by heating without using additional solder. Second, we studied interdiffusion and the interfacial reaction during high-temperature storage of 95Pb5Sn solder bumps and 37Pb63Sn pre-solder in flip-chip solder joints. The reaction conditions included aging at 100, 130, 150, and 175℃ for times as long as 4000 hr. Third, this study also investigated the effect of the thermal stress in flip-chip solder (37Pb63Sn) joints. The reaction conditions included multiple temperature cycling test (TCT) between -55 to 125℃. In the reflow reaction, we found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cuplike structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the UBM/95Pb5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu atoms to the UBM/95Pb5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu0.6Ni0.4)6Sn5. In the solid-state reaction, we found that Cu6Sn5 and Cu3Sn formed on the board side and (Ni,Cu)3Sn4 formed on the chip side after 100 h of aging. After 2000 h of aging at 175℃, the Ni under-bump metallization (UBM) was exhausted. This caused the (Ni,Cu)3Sn4 layer at the chip-side interface to be converted gradually into (Cu0.6Ni0.4)6Sn5. We also found that the consumption of the Ni UBM was faster than when eutectic SnPb solder was used for the entire joint. Nevertheless, the consumption of Cu on the substrate side was slower than when pure eutectic SnPb solder was used for the entire joint. We also reported on the highly interesting microstructural evolution from a fine eutectic to a coarse laminar pattern caused by the cycling thermomechanical stress in eutectic PbSn flip-chip solder joints. The temperature was cycled between -55 and 125℃ for up to 2000 cycles. The shear strain on the corners joints, which experienced the maximum thermomechanical stress among all the solder joints in a flip-chip package, was estimated to be 0.13 for each cycle. A coarse laminar pattern, made up of the Pb-rich phase and the Sn-rich phase, gradually developed during the temperature cycling with phase boundaries that were approximately parallel to the direction of the shear stress. It is argued that the laminar pattern had developed in such a manner that the material with the lowest yield stress (the Pb-rich phase) could align itself with the direction of the shear stress. Because continuous soft layers were arranged in a direction that was approximately parallel to the direction of the shear stress, the stored deformation energy could be dissipated more efficiently. The least section reports on the Ni/95Pb5Sn/Cu ternary diffusion couples were used to investigate the cross-interaction between Ni and Cu across a layer of 95Pb5Sn solder. High-lead solder layers with thickness of 100 or 400 μm was electroplated over Cu oils. A pure Ni layer (20 μm) was then deposited over the as-deposited high-lead solder surface. The diffusion couples were then aged at 150 to 250℃ for different periods of time. With this technique, the diffusion couples were assembled without experiencing any high temperature process, such as reflow, which would have accelerated the interaction and caused difficulties in analysis. This study revealed that the massive spalling also occurred during aging even though reflow was not used. The massive spalling began with the formation of micro-voids. When the micro-voids congregated into large enough voids, the intermetallics compounds (Cu3Sn) started to spall from the interface. This spalling phenomenon occurred sooner with increasing temperature and decreasing solder volume.

並列關鍵字

flip chip ； interfacial reaction ； high-lead solder ； composites solder ； spalling ； temperature cycling test

參考文獻

[BAK] H. Baker (ed.), ASM Handbook v.3: Alloy Phase Diagrams, ASM,

[BLA] H. D. Blair, T.Y. Pan, J. M. Nicholson, 1998 Electronic Components and Technology Conference, p.259, 1998.

[BOL] S. C. Bolton, A. J. Mawer, and D. Mammo, Intl. J. Microcircuit and Electronic Packaging, 18, p.109, 1995.

[CHAN1] C. C. Chang , Y. W. Lin, Y. S. Lai, and C. R. Kao, J. Electron. Mater., 38, p.2234, 2009.

[CHAN2] C.C. Chang, Y.W. Wang, Y.S. Lai, and C.R. Kao, J. Electron. Mater. in press DOI: 10.1007/s11664-010-1186-4 (2010)

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覆晶封裝中銲料組成對兩界面反應之影響

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