運用於低功率FPGA之電壓調降及基體偏壓最佳化技術

隨著製程技術進步,製程變異成為功率以及時序分析方式的一個障礙。而統計時序分析成為眾多處理設計不確定性的一種技術。統計時序分析中需要最大計算量是一種稱為緊密機率 (Tightness Probability)的技術。這種技術能將兩個隨機變數在機率上的大小表示出來。但是由於訊號相互獨立的這項假設導致計算上顯著的誤差。我們說明了緊密機率是如何被不同的計算方式影響,並且提出解決方案。我們並進一步延伸我們的研究至如何用定性 (Deterministic)與統計的方式最小化FPGA的功率消耗。 FPGA因為有可重配置性(Reconfigurability)與快速上市的特性而廣泛地被運用在 IC設計上。但是因為功率與面積的因素導致它不適合手持式與低功率等產品。有許多的低功率技術不斷地被提出,像是具有彈性輸入個數的LUT、電源下降、基體偏壓、低漏電流靜態隨機存取記憶體、功率閘控和雙臨界電壓。在此研究中,適應性電源與適應性基體偏壓被運用在同時降低動態與靜態功率。這些方法將會運用在後晶片(Post-silicon)最佳化。如果製程變異並不顯著或是無法獲得,我們就可採用幾何規劃的定性方式來降低功率消耗。對於統計最佳化而言,因為漏電流有著指數的數學形式,所以難以化為凸型最佳化。在這種情況下,如果時序沒有過於嚴苛,則時序與功率被逼近為線性規劃並且可被有效率地解出。

關鍵字

緊密機率；功率最佳化； FPGA ；幾何規劃；統計最佳化

並列摘要

As technology scales, process variation impedes the accuracy of conventional power and delay analysis. Statistical static timing analysis (SSTA) is one of the reactions to cope with the design uncertainty. The computation of tightness probability is one of the most important elements in SSTA. Given two random variables, it calculates the probability that the value of one is greater than that of the other. However, it suffers from significant computational error due to the signal independence assumption. We show how tightness probability is affected by different computation orders, and propose a solution to it. We further extend our work to FPGA power minimization under deterministic and statistical timing constraints. FPGA is widely used in IC design due to its re-configurability and fast time-to-market capability. However, the power and area issues make it not suitable for hand-held and other low power devices. Many techniques are proposed to reduce FPGA power consumption, such as .flexible LUT sizes, supply voltage scaling, body biasing, low leakage SRAM, power gating, and dual threshold voltage. In this work, adaptive supply voltage and adaptive body biasing are applied to reduce power, including both dynamic and leakage power. They are then adopted in a post-silicon optimization. If the process variation is not significant or not available, the deterministic optimization, which can be formulated as geometric programming in a convex form, can be applied. For statistical optimization, leakage power is in exponential form and is hard to formulate in convex optimization. In this case, timing and power are approximated with linear programming and can be solved efficiently with small approximation error if the timing constraint is not too tight.

並列關鍵字

tightness probability ； power optimization ； FPGA ； geometric programming ； statistical optimization

參考文獻

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運用於低功率FPGA之電壓調降及基體偏壓最佳化技術

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