運用相位誤差偵測器之鎖相迴路時脈產生器

PLL Clock Generator with Phase Error Detector

賈儒林(Ju-lin Chia)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.00491

摘要

本論文探討以深次微米金氧半(CMOS)技術實現之鎖相迴路(PLL),針對以下兩主題提出新的方法.第一,使用相位誤差偵測器進行相位誤差偵測.第二,利用相位誤差偵測值與數位控制延遲電路進行校正,取得相位誤差最佳化
我們先討論鎖相迴路頻寬最佳化問題,首先,若要減少輸出信號受輸入的雜訊的影響,則迴路的頻寬要愈小愈好,其次,若要減少輸出的信號受內部振盪器的雜訊影響,則迴路的頻寬要愈大愈好.此二種要求是相互抵觸的,需要某種程度的妥協.
當鎖相迴路系統頻寬取得最佳化時,用於實體晶片製造下,因製程過程會有偏移而產生誤差,因而造成相位誤差.利用相位誤差偵測器,可取出相位誤差平均值.
我們提出了一個校正系統.此系統利用上述平均值可以校正鎖相迴路的相位誤差,取得其最佳化.最後運用實作的晶片去驗證我們所提出的理論確實可達到我們預計的效果.

關鍵字

鎖相迴路 ； 相位誤差偵測器

並列摘要

This thesis describes with the PLL of a CMOS technique, and put forward two topics. First, use phase error detector circuit to detect the phase error. Second, use the phase error detector and digital control delay line (DCDL) circuit to correct the phase error of the PLL.
We discuss the PLL bandwidth optimization problem. first, if reduce the noise influence that the output’s signal to the out of chip, then the bandwidth of the PLL want to be the smaller the better, the next in order, if reduce the noise influence that the output's signal to the inner part, then the bandwidth of the PLL want to be the bigger the better. The two kinds of requests is what conflict with mutually, needing the compromise of a certain degree.
When PLL system bandwidth obtains the optimization, being used for the chip manufacturing will be partial to move and produce the error margin because of the manufacturing process, cause the phase error. Making use of the phase error detector circuit can take out the phase error average values.
We put forward corrects the system. This system makes use of the above the average value can correct the PLL phase error. Finally, the chip made use of to make actually identifies we put forward of theories can reach the result that we anticipate really.

並列關鍵字

Phase Error Detector ； PLL

參考文獻

[2] B. Razavi, Monolithic phase-locked loops and clock recovery, IEEE press, 1996.

[3] F. M. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.

[4] M. V. Paemel, “Analysis of a charge-pump PLL: a new model,” IEEE Trans. Commun., vol.42, no. 7, pp. 2490-2498, July 1994.

[7] A. Stevens, R. Van Berg, J. Van der Splegel, and H. Williams,“A time-to-voltage converter and analog memory for colliding beam detectors,”IEEE J. Solid-State Circuits, vol.24, pp. 1748-1752, DEC. 1989.

[8] M. Tanaka, H. Ikeda, M. Ikeda, and S Inaba,“ Development of a monolithic time-to-amplitude converter for high precision TOF measurement,”IEEE Trans. Nucl. Sci, vol. 38, pp. 301-305, Apr. 1991.