本篇論文是利用二進位搜尋演算法電路控制器加快鎖定頻率速度,並 利用數位類比轉換器以及整流器來實現寬頻率調變範圍之全數位式 鎖頻迴路。其控制電壓範圍由0.7伏至1.6伏,使得頻率調變範圍由 30MHz至480NMHz。其中本篇論文使用之電壓控制震盪器在操作頻 率480MHz下時其RMS jitter小於0.21%,並使用台積電0.18微米製程 其總晶片面積為0.31平方毫米。
This paper proposes a wide frequency tune range all-digital frequency locked loop (ADFLL) with a successive approximation register-controlled (SAR) architecture. It uses a digital to voltage converter (DAC) and regulator to provide a wide supply voltage range from 0.8v to 1.6v for a wide operational tune frequency range of 30MHz to 480MHz. The proposed voltage controlled oscillator (VCO) performance has a less than 0.21% RMS jitter at 480 MHz output frequency. The core area of ADFLL is 0.31mm2 in a 0.18μm CMOS process.