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  • 學位論文

1至16倍速DVD燒錄器寫入時脈訊號產生器

A Clock Generator for 1X~16X DVD Recorder Write Pulse

指導教授 : 黃弘一
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摘要


本篇論文是利用二進位搜尋演算法電路控制器加快鎖定頻率速度,並 利用數位類比轉換器以及整流器來實現寬頻率調變範圍之全數位式 鎖頻迴路。其控制電壓範圍由0.7伏至1.6伏,使得頻率調變範圍由 30MHz至480NMHz。其中本篇論文使用之電壓控制震盪器在操作頻 率480MHz下時其RMS jitter小於0.21%,並使用台積電0.18微米製程 其總晶片面積為0.31平方毫米。

並列摘要


This paper proposes a wide frequency tune range all-digital frequency locked loop (ADFLL) with a successive approximation register-controlled (SAR) architecture. It uses a digital to voltage converter (DAC) and regulator to provide a wide supply voltage range from 0.8v to 1.6v for a wide operational tune frequency range of 30MHz to 480MHz. The proposed voltage controlled oscillator (VCO) performance has a less than 0.21% RMS jitter at 480 MHz output frequency. The core area of ADFLL is 0.31mm2 in a 0.18μm CMOS process.

並列關鍵字

ADFLL DAC SAR VCO

參考文獻


[1] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, ‘‘An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,’’ IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr., 1995.
[2] T.-C. Chao and W. Hwang, ‘‘A 1.7mW all digital phase-locked loop with new gain generator and low power DCO,” in Proc. IEEE Int. Symp. Circuit and Systems, 2006, pp. 4867-4870.
[3] P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, ‘‘A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,’’ IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-285, Jun., 2006.
[4] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, ‘‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,’’ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan., 2008.
[5] M. G. Johnson and E. L Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct., 1988.

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