嵌入式晶體振盪器之時脈產生器設計

Design of A Clock Generator Based on Embedded Silicon Oscillator

楊智超

指導教授 ： 李鎮宜

國立交通大學/電機學院/電機學院IC設計產業專班/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00889

摘要

隨著製程技術的提升，電晶體尺寸持續縮小化，電壓、製程和溫度的對電路產生的偏移，以及市場對於低成本、低功率消耗以及高製程整合的大型積體電路需求呈現指數的上升，使得設計日益困難。於現今的電子系統中，石英晶體振盪電路是唯一沒有被整合在積體電路中的元件之一。然而，石英晶體振盪電路不相容於製程的結果，造成額外的製造成本、電路層級的整合體積與高功率消耗。

本論文提出一種基於嵌入式晶體振盪器之全數位時脈產生器。所提出的全數位式鎖相迴路可以使嵌入式晶體振盪器的輸出獲得更準確的頻率，而且可以確定嵌入式晶體振盪器不需要使用任何外在的元件，仍然有能力去對頻率誤差做校正。另外，全數位式鎖相迴路在工作於5百萬赫茲時僅消耗125uW。另外，為了達成某些特殊的脈波寬度以及適用於低功率消耗、低傳輸速率的通訊系統，本論文提出一種全數位式脈波寬度可控制迴路及工作週期調整之電路，可接受輸入時脈的頻率從5百萬到6億赫茲，而且不需要任何的查表。輸出時脈的工作週期不但可以產生50%的工作週期，還可以調整從10%到90%之間於每隔10%的工作週期。

關鍵字

時脈產生器 ； 嵌入式晶體振盪器

並列摘要

With the deep sub-micron CMOS technology continues to scale, the presence of the voltage, process and temperature variations make the circuit design more difficult. Furthermore, the market demand for low-cost, lower power consumption and higher integration density VLSI systems have grown exponentially. The quartz crystal (XTAL) oscillator is one of the last components in electronic systems that have yet to be integrated. However, the incompatibility in the process results in extra cost and volume in the board-level integration and, hence, large power is wasted from the external crystal oscillator.

This thesis proposes an all-digital clock generator based on embedded silicon oscillator. The proposed all-digital phase-lock-loop (ADPLL) can achieve more accuracy in output frequency of eCrystal. This ADPLL can ensure the embedded silicon oscillator is able to calibrate the frequency error without any external component. Moreover, it has lower power consumption which consumes 125uW at 5MHz. The all-digital pulse-width-control-loop (ADPWCL) with adjustable duty cycle is adopted to meet the demand for pulse-width-specific, low power consumption and low data rate communication systems. This ADPWCL provide a wide operation range without look-up-table, covering from 5MHz to 60MHz operation range. The output clock is not only achieved 50% duty cycle, but can also be adjusted duty cycle from 10% to 90% in steps of 10%.

並列關鍵字

ADPLL ； ADPWCL

參考文獻

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