利用TSMC 0.18μm CMOS 製程實現2Gb/s低電壓差動訊號之高速資料接收器

2Gb/s Low-Voltage Differential-Signal(LVDS)Data Receiver Using TSMC 0.18μm CMOS Technology

林冠賢(Lin Kuan-Hsien)

指導教授 ： 陳自強

國立中正大學/工學院/電機工程學系/碩士(2013年)

摘要

隨著消費性電子產品需求量大增，使得矽智財 (Intellectual Property core IP)積體電路模組之複雜度與傳輸資料量大幅提高。為了減少功率消耗及達到資料高速傳輸，目前低電壓差動訊號(Low-Voltage Differential Signal LVDS)傳輸標準介面已被提出。低電壓差動訊號傳輸技術採用低電壓擺幅差動訊號傳輸串列資料，具有高速、低功率消耗與高抗雜訊干擾等優點。
本論文主要研究方向是利用低電壓差動訊號傳輸技術，以市面上相關完整系統IP產品應用層面為考量，設計出2Gb/s低電壓差動訊號(LVDS)之高速資料接收器。此接收器由伸縮組態放大器、遲滯比較器、適應性調整延遲電路及雙緣觸發序列平行轉換器所組成。接收器前端設計為高增益頻寬積伸縮組態放大器與高速遲滯比較器，其前端之序列傳輸訊號透過後端雙緣觸發序列平行轉換器轉換成並列輸出12位元，可使接收器達到雙倍資料傳輸率輸出。另外，接收器利用適應性調整延遲電路補償高速序列傳輸訊號相位差，並與接收器系統時脈同步。吾人所設計之低電壓差動訊號接收器採用國家晶片系統中心(CIC)所提供的台積電 TSMC 0.18μm 1P6M CMOS 標準製程，進行電路設計模擬與下線製作。佈局後模擬結果顯示單通道接收器的傳輸速度可達到2Gb/s，接收器消耗功率為114mW，其八通道低電壓差動訊號接收器系統傳輸速度可達到1.2Gb/s，接收器消耗功率為478mW。以上模擬結果驗證功能皆正確無誤，且已下線成功。

關鍵字

雙緣觸發序列平行轉換器 ； 適應性調整延遲電路 ； 遲滯比較器 ； 低電壓差動訊號(LVDS)接收器IP ； 伸縮組態放大器

並列摘要

With increasing demand for consumer electronics products, such Intellectual Property (IP) integrated circuit modules tend to be complicated and operate at high- speed rate. In order to reduce power consumption and to achieve high-speed data transmission, nowadays Low-Voltage Differential Signal (LVDS) transmission standard interfaces have been widely used. LVDS technology uses low-voltage swing differential signals to transmit serial data, and has advantages of high speed, low power consumption and high noise immunity.
This thesis mainly utilizes LVDS technology and takes into consideration from application level of IP products to design 2Gb/s LVDS high-peed data receiver. This receiver includes telescopic amplifier, hysteresis comparator, adaptive phase delay adjustment and double-edge trigger de-serializer. In this thesis, the receiver of which front-end design has high gain-bandwidth product telescopic amplifier and high-speed hysteresis comparator adopts the double-edge trigger de-serializer to convert serial data to parallel output at 12 bits. It can achieve double data throughput rate of LVDS receiver output. On the other hand, the receiver involves an adaptive phase delay adjustment in which it compensates the phase difference that high-speed serial transmission signals of the receiver can synchronize with a system clock. The proposed 2Gb/s LVDS receiver has been fabricated by the TSMC 0.18μm 1P6M CMOS process provided by (CIC). Post-layout simulation results show that data transmission speed of one channel of the LVDS receiver is up to 2Gb/s where the power consumption is 114mW. In addition, the data transmission speed of the eight- channel LVDS receiver is up to 1.2Gb/s with the power consumption of 478mW. The simulations verify its function working, and has been successful taped out.

並列關鍵字

double-edge trigger de-serializer ； hysteresis comparator ； Low-Voltage Differential Signal (LVDS) data receiver IP ； telescopic amplifier ； adaptive phase delay adjustment

參考文獻

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