以0.18um CMOS積體電路技術設計支援大部份MIPS指令的低分支代價處理器

A Low Branch Penalty Processor Supporting Most MIPS Instructions in 0.18um CMOS Technology

張弘琦(Hung-Chi Chang)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10468

摘要

自從電腦被發明之後，我們一直在尋找能夠提升處理器效能的方法。但由分支指令所產生出的週期代價始終還是個問題。因此，這篇論文主要是在陳述如何實現一個低分支代價處理器的電路。

我們所用的架構主要是基本的MIPS五階層管路處理器。我們將這架構分為兩個部份: 功能區塊和控制區塊。功能區塊是負責各階層的運算，而控制區塊則是負責控制整個晶片，讓這個晶片能夠正確的執行每個步驟。另外，我們也在裡面介紹了三種在執行中會產生的危障(結構危障、資料危障和分支危障)和解決它們的方法。我們也會介紹分支預測單元和分支目標緩衝單元。

我們使用了 cell-based流程來實現我們的晶片。我們也在其中介紹了這個讓我們能夠由設計到製作出晶片的cell-base流程的一些主要重點。然後我們會展示出一些模擬結果。

我們是用聯電0.18um CMOS製程來製作這個晶片，最後我們會展示一些量測結果。這個晶片最高可在65MHz下工作且能夠支援37個指令，它的面積為1765.74(um) x 1652.32(um)。

關鍵字

分支 ； 預測 ； 處理器

並列摘要

Since the first computer is invented, we are seeking for ways to raise the performance of processors. But the penalty caused by branch instruction is still a problem. Therefore, this thesis mainly describes the implementation of a low branch penalty processor.
The structure we used is basically based on the basic and classic five-stage processor that would be introduced along with its five stages. We separate this structure into two parts: functional blocks, which are the blocks that responsible for the operations in each stage, and the control blocks, which are in charge of the control of the whole design so that the execution flow could work correctly. Besides, the three kinds of hazards (structural hazard, data hazard, and branch hazard) and the method to solve them are also referred. The branch predictor and branch target buffer are also presented.
We took the cell-based design flow as our implementation way. We also show the main point of this cell-based design flow, the way we transform a design into a chip. And then we present the simulation results of the design.
UMC 0.18um 1p6m CMOS technology is used to implement this chip. At last we show the measurement result. This chip can work up to 65MHz with its area of
1765.74(um) x 1652.32(um) and support 37 instruction sets.

並列關鍵字

branch ； prediction ； MIPS ； processor ； 0.18um

參考文獻

[1] J.L. Hennessy and D.A. Patterson “Computer Organization & Design-The Hardware/Software Interface”

[2] J.L. Hennessy and D.A. Patterson “Computer Architecture, A Quantitative Approach”, 2003.

[3] Karthik Thangarajan, Wagdy Mahmoud, Esther Ososanya, Pic Balaji “Survey of Branch Prediction Scheme for Pipelined Processors” System Theory, 2002, 18-19 March 2002,Pages: 324-328

[4] Tse-Yu Yeh, Yale N.Patt “Alternative Implementations of Two-Level Adaptive Branch Prediction”1992 ACM 0-89791-509-7/92/0005/0124

[7] A.M. Gonzalez, “A Survey of Branch Techniques in Pipelined Processors,” Microprocessing and Microprogramming, pp: 243-257 Vol. 36, 1993.