- 學位論文
以0.18μm CMOS製程研製超寬頻系統低功耗之微型化接收機及2.4GHz陣列組合高功率放大器
The Design of Low Power RF Receiver for Ultra-wideband System and Array High Power Amplifier Using 0.18μm CMOS Process
摘要
本論文之UWB接收機降頻器是利用TSMC 0.18μm 1P6M CMOS製程研製，其中包含三個實際製作完成之電路為3~10GHz寬頻低雜訊放大器與3~10GHz具主動balun低電壓寬頻混頻器與2.4GHz陣列組合高功率放大器。3~10GHz 低雜訊放大器是採用改良式的chebyshev來達成輸入寬頻的匹配，配上Current-reused的架構，再搭配Peaking Inductor的技術，來達到寬頻、低雜訊指數、低功耗以及高增益等目標，此IC量測結果功率消耗為7.52mW、平均增益為10±1.5dB、雜訊指數(Min)為3.9dB，S11<-10dB及S22<-12B。3~10GHz具主動balun低電壓寬頻混頻器是採用Folded-switching mixer架構與後級主動Balum器之整合，來達到寬頻、低偏壓以及高而平坦的增益等目標。此電路模擬結果平均增益為 22±0.5dB、雜訊指數為(DSB)7.7~11.8dB，功率消耗為18.06mW，IIP3為-22dBm，P1dB為-30dBm。2.4GHz陣列組合高功率放大器設計主要以全積體化功率放大器為目標構想用陣列並排的方式，將所有的放大器匯集的電流結合起來，並運用NMOS與PMOS之間的正負訊號轉換省下驅動級的面積，這樣可以使整體的面積比起傳統的功率放大器的結合還來的小，此電路模擬結果輸出功率為26dBm、增益為11dB、P1dB為16dBm、PAE為15.4%、S11為-18.7dB、S22為-13.1dB。
並列摘要
This paper uses a TSMC 0.18 μm CMOS process to design a receiver for UWB systems. Three manufactures were commissioned to create the electric circuits 3~10GHz LNA, 3~10GHz mixer, and 2.4GHz power amplifier array. To achieve the goals such as a wide-band frequency, low power consumption, low noise figure, and high returns, the 3~10 GHz LNA adopts the current-reuse structure and utilizes a improved chebyshev and peaking inductor technology. The measurement results demonstrate the following performances of the design: The total power consumption is 7.52 mW under a 1.2 V supply voltage; the forward gain is 10±1.5 dB for a 3~10 GHz wideband frequency; the noise figure average (Min) is 3.9 dB; the input return loss is under -10dB, and the output return loss is under -12dB. Additionally, for the portion of the mixer that uses the folded-switching mixer with active balum for the low voltage supply, the forward gain is 22±0.5 dB for a 3~10 GHz wideband frequency; the noise figure(DSB) is 7.7~11.8 dB; the power consumption is 18.06mW; the IIP3 is -22dBm and the P1dB is-30dBm. 2.4GHz array of high power amplifier will combine all of the amplifier brings together the current. And the use of NMOS and PMOS between positive and negative signals into the save area of the driver stage, and this could make the whole area than traditional power amplifier combination of small. This circuit simulation result outpower power is 26dBm; the gain is11dB; the P1dB is 16dBm; the PAE is 15.4%; S11 is -18.7dB and S22 is -13.1dB.