應用於超音波影像之多通道低電壓差動訊號接收器自我同步校正機制

Self-Synchronization Mechanism Of Multichannel LVDS Receiver For Ultrasound Image

張智偉(Chih-Wei Chang)

指導教授 ： 陳自強

國立中正大學/工學院/電機工程學系/碩士(2015年)

摘要

隨著消費性電子產品需求量大增，使得矽智財積體電路模組之複雜度與傳輸資料量大幅提高。低電壓差動訊號傳輸標準介面的技術則是因應低功耗及高速資料傳輸。低電壓差動訊號傳輸技術採用低電壓擺幅差動訊號傳輸序列資料，具備高速、低功率消耗與高抗雜訊干擾等優點。
本論文主要研究方向是利用低電壓差動訊號傳輸技術，以市面上相關完整系統IP產品應用層面為考量，設計出匹配1.2Gb/s八通道低電壓差動訊號高速資料接收器模組之同步機制。其前端之序列傳輸訊號透過接收器轉換成並列輸出12位元，結合同步控制電路進行同步校正以正確還原傳送器所傳送之資料。
吾人所設計之多通道低電壓差動訊號接收器自我同步校正機制採用國家晶片系統中心所提供的台積電 TSMC 0.18μm 1P6M CMOS 標準製程，進行電路設計模擬與下線製作。佈局後模擬結果顯示八通道接收器的傳輸速度可達到1.2Gb/s。發射Ramp訊號的測試下，所提出之同步控制電路可於FPGA正確地將訊號接收並還原。以上模擬結果驗證功能皆正確無誤，且已下線成功。

關鍵字

適應性相位調整電路 ； 低電壓差動訊號接收器IP ； 序列器-解序列器 ； 雙緣觸發序列平行轉換器 ； 同步控制電路

並列摘要

With the increasing demand for consumer electronics products, such Silicon Intellectual Property integrated circuit modules tend to be complicated and transfer large amounts of data. The technology of Low-Voltage Differential Signal (LVDS) transmission standard interface is adapted to low power consumption and high-speed data transmission. The technology of LVDS uses low-voltage swing differential signals to transmit serial data, and has advantages of high speed, low power consumption and high noise immunity.
This thesis mainly utilizes LVDS technology and takes into consideration from application level of IP products to design the synchronization mechanism to match the 1.2Gb/s eight-channel low-voltage differential signal high-speed data receiver module. The sequence signals of front-end transmission convert into a 12-bit parallel word by the receiver, and the synchronization control circuit does synchronization correction to restore the data of the transmitter.
The proposed Self-Synchronization Mechanism Of Multichannel LVDS Receiver has been fabricated by the TSMC 0.18μm 1P6M CMOS process provided by Chip Implementation Center. Post-layout simulation results show that data transmission speed of eight-channel of the LVDS receiver is up to 1.2Gb/s. The proposed synchronization control circuit can be achieved for the ramp pattern test in the FPGA. The simulations verify its function working, and has been successful taped out.

並列關鍵字

double-edge trigger de-serializer ； adaptive phase adjustment ； low-voltage differential signal data receiver IP ； serializer-deserializer ； synchronization control loop

參考文獻

[10] 林冠賢，「利用TSMC 0.18 μm CMOS 製程實現2Gb/s 低電壓差動訊號之高速資料接收器」，國立中正大學碩士論文，民國一百零二年八月。

[11] 楊欣翰，「低功率多通道接收器與數位計算模組」，國立中正大學碩士論文，民國一百零二年八月。

[12] F. Lin, J. Miller, A. Schoenfeld and R.-J. Baker, “A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 565-568, Apr. 1999.

參考文獻

[1] PHY Interface for PCI Express – Intel, http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/phy-interface-pci-express-sata-usb30-architectures.pdf.