邊緣合成延遲鎖定迴路之設計與相位雜訊分析

Design and Phase Noise Analysis for Edge-Combining DLLs

廖芳仁(Fang-Ren Liao)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2012年)

https://doi.org/10.6342/NTU.2012.01027

摘要

本論文將討論邊緣合成延遲鎖定迴路的輸出突波改善、相位雜訊分析以及不規則延遲的校正之相關議題。相較於鎖相迴路頻率合成器，延遲鎖定迴路之頻率合成器有著較小的晶片面積、較低的雜訊累積以及因為倍頻而有較寬的輸出頻率之優點。然而，邊緣合成延遲鎖定迴路所遭遇到的主要問題則是因為迴路裡面所產生的靜態相位偏移以及在電壓控制延遲線裡面的不規則延遲所造成的輸出突波。因此在論文的第二章裡，於CMOS 90nm製程下，我們將設計一個可以快速切換頻率以及輸出頻率為0.45GHz到5.4GHz之邊緣合成延遲鎖定迴路。使用電流分流之電荷幫浦來減低相位偵測器其閒置區間的電流不匹配，如此一來，相對於使用傳統的電流切導電荷幫浦，其輸出突波在倍頻數為6、3和2的情況下分別有著9.1 dB、6.7 dB以及15.4 dB的改善。

儘管有很多研究致力於邊緣合成延遲鎖定迴路的設計，但是相對於鎖相迴路，幾乎沒有任何文獻提供其倍頻輸出的相位雜訊分析。傳統上，邊緣合成延遲鎖定迴路被歸類為相位重對齊鎖相迴路的一個特例，其相位偏移因子beta為1，所以相位重對齊鎖相迴路的閉迴路雜訊模型就被使用來解釋邊緣合成延遲鎖定迴路。然而，邊緣合成延遲鎖定迴路的輸出頻率可以因為不同的邊緣合成次序而有所改變，所以如果使用不同數目的延遲邊緣或是不同間距的延遲邊緣來切換，其相對應的輸出相位雜訊會有所不同。因此，藉由將延遲鎖定迴路裡面的雜訊抖動疊加在其穩態的週期性邊緣合成輸出，在第三章則提出一個改良的相位雜訊模型。此雜訊理論揭露邊緣合成延遲鎖定迴路以及鎖相迴路的基本不同點，又此理論即使在倍頻數改變的情況下仍能成功的預測其輸出相位雜訊。

雖然藉由降低在迴路裡面所產生的靜態相位偏移可以改善輸出突波，在電壓控制延遲線裡面的不規則延遲也是很重要的一個問題。不規則延遲在傳統上可以用相對相位比較法或是絕對相位比較法來加以校正。由於在電路裡面缺乏一個精準的參考源，相對相位比較法相對於絕對相位比較法而言是更容易於實做的方式。然而，相對相位比較法的主要問題在於其用來比較延遲輸出間相位差的相位比較器會產生額外的比較誤差。相對於相對相位比較法，絕對相位比較法則是使用同一個比較路徑、相對於同一個參考延遲元件來校正相鄰延遲元件間的相位差，因而減低了因相位比較期間所可能造成的誤差。儘管如此，用於絕對相位比較法裡的參考延遲元件其精準度是個問題，用於參考的延遲元件其偏差會造成即使相鄰延遲元件間的相位差是一樣的，但在電壓控制延遲線的輸出訊號其回授相位會高於或低於2*pi，因此在第四章中提出一個共同校正延遲鎖定迴路的原型來解決此問題。

關鍵字

延遲鎖定迴路 ； 邊緣合成器 ； 倍頻器 ； 突波 ； 週期性穩態 ； 相位雜訊 ； 不規則校正

並列摘要

In this dissertation, design issues such as output spur reduction, phase noise analysis, and delay mismatch calibration for edge-combining DLLs are discussed. The DLL-based frequency synthesizer outperforms its PLL counterpart by smaller chip area, less noise accumulation, and wider output range due to the frequency multiplication. However, the main problem associated with the edge-combining DLL, is output spur, which is caused by the static phase offset in the DLL loop and delay mismatches among delay cells in the VCDL. In Chapter 2, an edge-combining DLL is designed in a CMOS 90-nm process that can switch frequency fast and cover 0.45 to 5.4 GHz output frequency. The current-splitting CP is proposed to reduce the current mismatch during the idle interval of the PD so that output spur achieves 9.1 dB, 6.7 dB, and 15.4 dB improvement as compared to the current-steering CP for the frequency multiplication of 6, 3, and 2, respectively.

Despite lots of works focused on the implementation of the edge-combining DLL, almost no work provides phase noise analysis at the frequency-multiplied output in contrast to PLLs. Conventionally, the edge-combining DLL is categorized as a special case of phase-realigned PLLs (RPLLs) by assuming that the phase-shift factor, beta, is 1. The closed loop noise model for the RPLL is then used to explain the edge-combing DLL. However, since the output frequency of the edge-combining DLL can be varied by changing the edge combining sequence directly, output phase noise will differ if a different number of or different spacing between edge transitions are adopted. A modified phase-noise model is proposed in Chapter 3 by superimposing the noise jitter from the DLL on the periodic steady-state solution at the edge-combining output. The derived noise theory then discloses the fundamental difference between edge-combining DLLs and PLLs. The success of the proposed theory is verified even if the frequency multiplication factor changes.

Although output spur can be improved by reducing the static phase offset in the loop, delay mismatches among delay cells in the VCDL are also important problems. Delay mismatches can be traditionally calibrated by using relative phase comparison or absolute phase comparison. Due to the lack of a precise reference in the circuit, relative phase comparison is supposed to be more realizable than the absolute one. However, the main issue for the relative phase comparison is that the external phase comparators, required to compare the phase difference between the adjacently delayed outputs, introduce extra comparison mismatches. As for absolute phase comparison, the phase difference between the adjacent stages is calibrated to the same reference delay cell by using the same calibration path, eliminating the possible mismatches during phase comparison. Nevertheless, the accuracy of the reference delay cell is an issue. The deviation of the reference delay cell may cause the output phase of the feedback signal larger or smaller than 2*pi, even if the phase differences among the delay cells are the same. A prototype common calibration DLL is proposed in Chapter 4 to solve this issue.

並列關鍵字

delay-locked loop (DLL) ； edge combiner ； frequency multiplier ； spur ； periodic steady state (PSS) ； phase noise ； mismatch calibration

參考文獻

[1] G. Chien and P. Gray, “A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 1996–1999, Dec. 2000.

[2] C. Kim, I. Hwang, and S. Kang, “A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator,” IEEE J. Solid-State Circuits, vol. 37, pp. 1414–1420, Nov. 2002.

[3] R. Farjad-Rad, W. Dally, H. Ng, R. Senthinathan, M. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits,vol. 37, pp. 1804–1812, Dec. 2002.

[4] J. Zhuang, Q. Du, and T. Kwasniewski, “A -107dBc, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer,” in IEEE Custom Integrated Circuits Conference, pp. 301–304, Sept. 2003.

[5] S. Ye and I. Galton, “Techniques for phase noise suppression in recirculating DLLs,” IEEE J. Solid-State Circuits, vol. 39, pp. 1222–1230, Aug. 2004.