全數位延遲鎖定迴路及全數位鎖相迴路之設計與應用

Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop

王佑仁(You-Jen Wang)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01270

摘要

本論文描述以數位方式實現與應用類比延遲鎖定迴路與鎖相迴路。和類比延遲鎖定迴路與鎖相迴路比較，全數位延遲鎖定迴路與鎖相迴路具有容易做製程轉移，節省被動元件組成的濾波器，以及快速鎖定的優點。因此以數位方式實踐類比電路近期比較受到歡迎，像是延遲鎖定迴路，鎖相迴路，資料時脈回復電路以及頻率合成器。
本論文包含四個電路：全數位的延遲鎖定迴路，鎖相迴路，資料時脈回復電路以及頻率合成器。首先，提出一個可調整工作週期的全數位的延遲鎖定迴路。利用對輸入週期作時間到數位的轉換結果，輸出時脈的相位與工作週期可以被快速校正。而且輸出時脈的相位與工作週期可以在十個輸入週期內校正完成。
第二，提出一個操作頻率範圍從15KHz到1.39GHz的全數位鎖相迴路，而且輸出頻率的倍率可以從1倍到32768倍。此電路使用頻率記數與二元搜尋法來減少鎖定時間。而且提出一個可應用在寬操作頻率範圍的可程式化除頻器。另外，利用一對電容之間的差值進行調變數位振盪器的頻率，使得數位振盪器的時間解析度改善到0.013微微秒。
第三，提出一個傳輸速率從6.34Mbps 到1.5Gbps的全數位資料時脈回復電路。提出的頻率搜尋演算法減少頻率鎖定時間，而且確保在寬頻操作下不會發生諧波鎖定。此時料時脈回復電路以90奈米互補金屬氧化矽製程實現，部分電路利用數位合成的方式使面積縮小為0.00368平方毫米，比之前發表過的文獻小。
最後，提出一個具有相位誤差消除、校正與修正迴路的全數位頻率合成器。提出的相位誤差、消除與校正迴路減少除小數造成的邊頻與相位雜訊。而且相位誤差消除、校正與修正迴路採用數位合成的方式節省電路面積。另外，使用調變一對容值差異小的電容之控制電壓差改進了頻率解析度。而且提出一個高倍率的時間放大器，減輕D型觸發器的偏移校應。

關鍵字

全數位 ； 延遲鎖定迴路 ； 鎖相迴路 ； 資料時脈回復電路 ； 頻率合成器 ； 數位控制振盪器

並列摘要

This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migration, no passive loop filter needed, and fast locked time. Therefore, digital equivalent implementations of analog circuits are more popular, such as delay-locked loop (DLL), phase-locked loop (PLL), clock and data recovery circuit (CDR), and frequency synthesizer.
There are four works in this thesis: all-digital DLL, PLL, CDR and frequency synthesizer. First, an all-digital DLL with adjustable duty cycles is proposed. The phase and duty cycle of output clock are fast adjusted by the time-to-digital conversion result of the input period. Therefore, the phase alignment and the duty cycle of output clock are assured in 10 cycles of input clock.
Second, a 15KHz-1.39GHz all-digital PLL with frequency multiplication by 1 to 32768 is presented. The frequency counting and binary searching methods are applied to reduce the locked time. And a programmable divider is proposed for wide frequency range applications. Furthermore, the timing resolution of the proposed digitally-controlled oscillator (DCO) is improved to 0.013ps by the capacitance difference among the varactors.
Third, a 6.34Mbps-1.5Gbps all-digital wide-range CDR circuit is presented. The proposed frequency-searching algorithm reduces the frequency locked time and eliminates the harmonic locking problem over wide-range data rates. The CDR circuit has been fabricated in 90nm CMOS process, and parts of this circuit is digital synthesized and reduce the area to 0.00368mm2, smaller than previous publish works.
Finally, an all-digital frequency synthesizer with cancellation, calibration, and correction loops is presented. The proposed cancellation, calibration and correction loops reduce the fractional spur and phase noise of output clock. And the cancellation, calibration and correction loops are digital synthesized to reduce silicon area. Furthermore, the frequency resolution of the proposed DCO is improved by adjusting the difference of control voltage between the two varactors with small capacitance difference. And a high-gain time amplifier is proposed to reduce the offset of D flip-flops.

並列關鍵字

all-digital ； Delay-Locked Loop ； Phase-Locked Loop ； Clock and Data Recovery Circuit ； Frequency Synthesizer ； Digital-Controlled Oscillator

參考文獻

[3] B. Razavi, “Design of integrated circuits for optical communications,” McGraw Hill, international edition, 2002.

[4] B. Razavi, “RF microelectronics,” Prentice Hall, 1998.

[5] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.

[6] Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, ”An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance’, IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.

[7] H. H. Chang, J. W. Lin, C.Y. Yang, and S. I. Liu, "A wide-range delay-locked loop with a fixed latency of one clock cycle", IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002.