利用動態相位控制機制之快速鎖定全數位鎖相迴路

An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking

莊昀蓁(Yun-Chen Chuang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.02402

摘要

本篇論文實現了一個利用動態時間窗來控制相位資訊的全數位鎖相迴路，實作上提出雙模式雙路徑的操作來達成快速鎖定與低時脈抖動的特性。補償相位的路徑利用動態改變除數的方式，而頻率的修正則由前饋路徑直接調變數位振盪器。除此之外，雙模式的設定使得迴路在鎖定後能切換至窄頻寬且妥善設計其阻尼係數。由於在鎖定過程中，鎖相迴路維持在一個較小的相位誤差，因此鎖定時間可有效地縮短；可程式化的數位濾波器設計也使得鎖定後的效能能夠獲得控制。在電路層面上，使用不對稱延遲單元減少在時序數位轉換器的功耗與面積，後端具有錯誤校正的編碼器可用來減輕時序放大電路的規格要求；數位振盪器的部分，則是選擇具有較細解析度與較佳相位雜訊之電感電容架構。因此，提出之系統架構可實現一低時脈抖動與快速鎖定的全數位鎖相迴路。
使用台積電0.18微米製程設計一應用於2.4 GHz頻帶之全數位頻率合成器。在5-25 MHz的跳頻距離下，鎖定時間皆小於5 us；中心頻率為2.49 GHz時，量測到的時脈抖動為1.93 ps，相位雜訊於100 kHz與1 MHz頻率偏移下分別為-79.6 dBc/Hz和-112.7 dBc/Hz，參考頻率突波於5 MHz頻率偏移下低於-50 dBc。整個鎖相迴路操作在1.8 V共花費10.35 mA電流，晶片面積為1.8 mm2。

關鍵字

全數位鎖相迴路 ； 快速鎖定 ； 時脈抖動 ； 數位振盪器 ； 時序數位轉換器

並列摘要

This thesis presents an all-digital phase-locked loop (ADPLL) featuring a dynamic phase compensation by a set of the auxiliary timing window. When frequency hopping occurs, the compensation scheme is implemented in both frequency and phase domain for fast settling. The detected phase error is continuously sent to the divider chain which changes the divider ratio, and directly modulates the frequency of the digital-controlled oscillator (DCO) through a digital feed-forward path at the same time. The proposed method allows the ADPLL maintaining a small phase error throughout the frequency acquisition process; thereby reducing setting time. Because of the switching mode operation, the mentioned techniques can solve the trade-off between low jitter and fast lock. An uneven-step time-to-digital converter (TDC) with an error correction encoder is implemented to relax circuit design and save power consumption. The DCO adopts the LC-based architecture because it has the finer tuning gain and better phase noise performance. The proposed ADPLL is implemented to optimize timing jitter and lock time.
The proposed technique is incorporated in the design of a 2.4 GHz ADPLL and fabricated in the TSMC 0.18 um CMOS technology. With less than 5 us lock time in hopping frequency from 5 MHz to 25 MHz, the measured rms jitter from a 2.49 GHz carrier is about 1.93 ps. The phase noise at 100 kHz and 1 MHz is -79.6 dBc/Hz and -112.7 dBc/Hz, respectively. The reference spur at 5 MHz offset is under -50 dBc. The whole circuit dissipates 10.35 mA from a 1.8 V supply and the chip area is 1.8 mm2.

並列關鍵字

all-digital phase-locked loop (ADPLL) ； fast locking ； timing jitter ； digital-controlled oscillator (DCO) ； time-to-digital converter (TDC)

參考文獻

[1] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in A Deep-Submicrometer CMOS Process,” IEEE Trans. Circuits Syst. II, vol. 50, no.11, pp. 815–828, Nov. 2003.

[2] R. B. Staszewski et al., “All-Digital PLL and Transmitter for Mobile Phone,” IEEE J. Solid-State Circuits, vol. 40, pp. 2469–2482, Dec. 2005.

[3] C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital Sigma-Delta Fractional-N Frequency Synthesizer with A Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circuits, vol. 43, pp. 2776–2786, Dec. 2008.

[4] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.

[5] N. A. D'Andrea and F. Russo, “A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis," IEEE Trans. on Communications, vol. 26, pp. 1355-1364, Sep. 1978.