具有工作週期校正能力的全數位快速鎖定延遲鎖定迴路

All-Digital Fast-Locking Delay-Locked Loop with Duty Cycle Correction

陳柏均(Bo-Jiun Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00627

摘要

隨著CMOS製程技術的發展和進步，最近幾年對於高速和高整合密度的VLSI系統的要求已經快速的上升。然而IC模組中的同步化無庸置疑地是重要的課題，也是高完美系統的瓶頸之ㄧ。鎖相迴路和延遲鎖相迴路已廣泛地被運用在解決同步的問題。由於結構上的不同，延遲鎖相迴路的兩大特性:無條件穩定跟快速鎖定，使得延遲鎖相迴路比較常被使用。此外，由於電壓控制延遲線上的抖動不會隨著時間大幅累積，延遲鎖項迴路也會提供比較好的抖動表現。而全數位的設計具有高攜帶性以及在它可以輕易轉移到不同的製程上。它高整合性、低消耗功率和低抖動的特性也很容易整合在數個系統之中。在雙倍取樣的系統中，例如靜態記憶體和類比到數位轉換器，具有50% 工作週期的訊號是非常重要。因此，我們需要工作週期校正器使得時脈的校正工作週期自動校正到50%。

這本論文中包含了兩顆全數位延遲鎖定回路和一顆全數位50%工作週期校正器的設計與實現。首先，一個全數位50% 的工作週期校正器被提出。這邊所提出的工作週期校正器的特色包括寬操作頻率範圍、寬輸入週期範圍和快速校正的時間。可接受的工作週期和頻率範圍分別為25% 到75% 和 250 百萬赫茲到600百萬赫茲。此外，此工作週期校正器可以減少功率消耗藉由關掉一半延遲單元。
第二，一個具有50%工作週期的快速鎖定全數位延遲鎖相迴路被提出。根據所提出的架構，它不只可以使輸入和輸出相位對齊，還可以將輸出訊號的工作週期校正到50%，它僅僅只花費四個週期，除此之外，重複使用的延遲線，不只扮演延遲單元也扮演時間數位轉換器的腳色，因此它可以大大減少面積和功率的消耗，可接受的工作週期和頻率範圍分別為40% 到60% 和 300 百萬赫茲到500百萬赫茲。
最後，一個寬範圍不用額外的啟動訊號的全數位延遲鎖相迴路在這裡被呈現。由於動態頻率偵測器，整個系統不需要一個外部的重新啟動訊號去重新啟動當輸入訊號頻率有很大的變化之時。這邊提出的二位元時間數位轉換器比傳統的時間數位轉換器可以更有效地減少硬體的消耗，這整個系統是一個閉迴路系統，所以它可以根據輸入電壓、溫度和製程的變異而調整。他操作的頻率範圍為62.5 百萬赫茲到625百萬赫茲，它只花四到六個週期即可達到鎖定。

關鍵字

延遲鎖相迴路 ； 全數位 ； 時間到數位轉換器 ； 工作週期校正器

並列摘要

With the evolution and continuing scaling of CMOS technologies, the demand of high speed and high integration density VLSI systems have the exponential growth recently. However, the synchronization problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high performance systems. Phase-locked loops (PLLs) and delay-locked loops（DLLs）have been widely employed for the purpose of synchronization. Due to the difference of their configurations, the DLLs are preferred for their unconditional stability and faster locking time than the PLLs. Additionally, a DLL offers better jitter performance than a PLL because noise in the voltage-controlled delay line (VCDL) does not accumulate over many clock cycles. The all-digital design has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into several systems. A clock with 50% duty-cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%.

This thesis contains three design and realization of the all-digital DLL and DCC circuits. First of all, an all-digital 50% DCC is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a faster correction speed. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The correction time is 8ns at 500MHz. Besides, this DCC can save power consumption by turning off half of the delay cells.
Secondly, a fast-locking all-digital DLL with 50% duty cycle is proposed. Based on the proposed architecture, not only the phase alignment of input and output clocks can be achieved, but also the duty cycle of the output clock can be corrected to 50%. It can synchronize in four cycles. Besides, the proposed delay line plays not only delay cells but also a time-to-digital converter (TDC). So it reduces active area and power effectively. The input frequency range can operate within 300MHz-500MHz. The accepted input duty cycle range is 40%-60%.
Thirdly, a wide-range anti-reset all-digital DLL is presented. The total system does not need any outside-reset signal to reset the system when the input clock frequency changes a lot, due to the dynamic frequency detector. The proposed binary TDC can reduce effectively hardware compared with a traditional TDC. Besides, the while system is a closed loop and it can track PVT variations. The input frequency range can operate within 62.5MHz-625MHz. It spends four to six cycles to get synchronization.

並列關鍵字

delay locked loop ； all-digital ； time-to-digital converter ； duty cycle corrector

參考文獻

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