適用寬頻操作且具有快速鎖定及低抖動特性之延遲鎖定迴路

A Wide-Range DLL-Based Frequency Multiplier with Fast-Locked and Jitter-Bounded Features

林盟峰(Meng-Feng Lin)

指導教授 ： 郭建宏

淡江大學/工學院/電機工程學系碩士班/碩士(2008年)

https://doi.org/10.6846/TKU.2008.00503

摘要

電路系統中的時脈訊號已越來越快，都是幾百MHz以上在高速的操作之下分佈在整個系統的時脈遭遇許多問題，這是些問題有時候會嚴重到影響整個系統的效能。因此對於整個系統的時脈同步和快速的鎖定頻率就非常的重要，時脈同步的技術通常使用鎖相迴路(PLL)或延遲鎖定迴路(DLL)去完成整個系統的整合。延遲鎖定迴路和鎖相迴路在現今無線通訊上有很多應用，例如:無線區域網路(WLANs)、行動電話及衛星通訊設備…等等，然而越來越多應用採用延遲鎖定迴路，主要原因是雜訊累積的問題，因為延遲鎖定迴路不會在壓控延遲線(VCDL)上累積雜訊，所以成為比較受歡迎的架構。他們功能在於鎖定相位，可以使電路的時脈同步並減少非理想效應所產生的偏差。由於延遲鎖定迴路具有穩定及雜訊不會累積的特性，所以比起鎖相迴路更廣泛地使用在許多應用上，如:時脈回復和本地震盪器電路，然而傳統架構的延遲鎖定迴路還是有缺點存在，例如鎖定範圍太小，鎖定時間太長…等等。改善延遲鎖定迴路這些缺點是個很有挑戰的研究，因此我們設計及實現延遲鎖定迴路。
在本論文裡亦將從快速鎖定(Fast-Locking)、寬頻操作(Wide-Range Operation)及低抖動(Low Jitter)三項特點同時進行考量，以達到改善的目標。
我們針對延遲鎖定迴路的缺點做改善，分別對其三項特點提出改善架構，提出的改善架構分別都改善了一項缺點，改善的架構特性敘述如下：
第一，根據延遲鎖定迴路輸入的頻率，我們提出了一個初始控制之可程式化的預先電壓設定電路(Programmable Charging Circuit)的機制給回授濾波器一個適當電壓來加速延遲鎖定迴路鎖定，鎖定時間都可被縮短至n個時脈週期的時間。
第二， 我們提出一個新的倍頻器，它能使用較少的元件來實現倍頻電路，以提升可操作範圍和應用。而新架構中的壓控延遲線使用虛擬差動延遲元件(pseudo-differential delay cells)的差動輸出當作倍頻器的輸入，使其得到接近50%的工作週期(duty cycle)時脈。
第三，我們利用雙延遲回授的架構，利用整個架構鎖定之後我們利用可調的延遲元件，在兩個相位頻率偵測器(Phase Frequency Detector，PFD)中產生一個虛擬的相位頻率偵測器，而這個虛擬的相位頻率偵測器具有一個虛擬死區(Pseudo Dead Zone)，使用這兩個相同的相位頻率偵測器去動作，輸入參考訊號會經過延遲，根據這個延遲讓兩個相位頻率偵測器會產生夾(Bounded)的動作，而這樣的架構特點是可以將鎖定後的輸出訊號具有比較小的抖動(Jitter)。
我們所提出改善的延遲鎖定迴路架構，利用0.18um1P6M CMOS 製程參數設計且操作電壓為1.8V，此電路可操作範圍為200MHz到2.2GHz。鎖定時間最少只需要6個週期，而且在250MHz的輸入參考頻率下的峰對峰值的抖動(Peak-to-peak jitter)為53.6ps，此時消耗的功率為31.6mW。此電路以完成佈局設計，核心佈局面積為0.34x 0.41mm2，此電路設計獲得國家晶片設計中心“A”等的審查結果。

關鍵字

延遲鎖定迴路 ； 假死區 ； 低抖動

並列摘要

With the extensive growth of the demand for high speed system, the required clock rate continues increasing. Thus, the issue of the clock synchronization among IC modules becomes more and more important, which results in a great improvement on the clock skew buffer and the data link technology. Though the Phase-locked loops (PLLs) provides a well locking loop for the clock synchronization, its inherent high-order loop and jitter accumulation nature make the high-accuracy PLL design difficult. On the other hand, the Delay-locked loops (DLLs) become more favourable than the PLL recently due to its no jitter accumulation in VCDL. DLLs are widely used in wireless telecommunications, such as wireless local area net-works (WLANs), mobile and satellite communications. DLLs and PLLs play an important role in the phase locked and the clock synchronization.
With the characteristics of stability and no noise accumulation, the DLL is more widely used than PLL in many applications, such as Time Recovery and Local Oscillator, which makes the DLL more and more important. However, there are still some disadvantages existing in traditional DLLs, such as small locking range, long locking time, etc. It is quite an interesting research for improving such disadvantages in traditional DLLs.
In this thesis, we design and implement the DLL. Thus, while designing the improved circuit architecture, the fast-locking, wide-range operation, and low jitter are three main considerations. And then for each feature, we have to further improve the original structure to achieve our goals. We present three methods to improve the whole architecture, which is shown as follows:
1. According to the frequency from the input to the DLL, we provide a proper voltage for the loop filter to accelerate the locking time with a programmable charging circuit (PCC). The locking time will be shortened by several times of the period of the clock, which makes a substantial reduction of locking time.
2. A novel frequency multiplier is presented. Less devices are used for the implementation, and thus, the operation range and application of such frequency multiplier will be raised.
3. The tow different delay feedbacks architecture is used. By means of such architecture, we use a tunable delay to generate a new PFD between PFD01 and PFD02 after SW2 turns on. The new PFD has a pseudo dead zone. With two identical PFDs, the input reference signal will be delayed, which will make those two PFDs bounded. With the pseudo dead zone, the output clock of the DLL will have small jitter than with single PFD. The architecture can make the locked output signal have less jitter.
The proposed DLL has been fabricated in 0.18um1P6M CMOS technology. From the simulation results, the proposed DLL-based frequency multiplier can operates in a wide range from 200MHz to 2.2GHz. Meanwhile, at the frequencies in such range, the minimum locking time of the DLL can be as less as six clock cycles. The simulated peak-to-peak jitter of the DLL is 53.6 ps at a frequency of 250MHz. The power consumption of the presented DLL is 31.6mW with a 1.8V supply voltage.

並列關鍵字

Delay-Locked Loop(DLL) ； Pseudo Dead Zone ； Low Jitter

參考文獻

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