具新型充電幫浦及突波消除電路之多頻率輸出延遲鎖定迴路設計

A Multi-Frequency Outputs Delay-Locked Loop with Glitch Elimination Circuit and New Charge Pump Circuit Design

王瀚賢(Han-Hsien Wang)

指導教授 ： 楊維斌

淡江大學/工學院/電機工程學系碩士班/碩士(2017年)

https://doi.org/10.6846/TKU.2017.01034

摘要

由於現今晶片的使用頻繁，製程技術也越來越先進，電路系統中的時脈訊號已越來越快，而在晶片內部的非理想效應會使相位產生誤差與延遲，這個問題可能會嚴重影響整個系統的效能。因此，數位系統電路整合的同步性也變得相對重要，尤其在高速運算的系統中，時脈偏移(clock skew)將是決定系統性能優劣的重要因素。時脈同步的技術通常透過鎖相迴路(Phase-Locked Loop，PLL)以及延遲鎖定迴路(Delay-Locked Loop，DLL)來消除時脈偏移，增加電路穩定度，可以產生穩定的輸出振盪頻率，以降低產品成本並增加產品競爭力。而延遲鎖定迴路(DLL)本身的抖動(jitter)以及穩定度方面表現比鎖相迴路(PLL)好。
延遲鎖定迴路(DLL)已經被廣泛運用在需要時脈操作的電路上，像是同步動態記憶體（SDRAM）、類比數位轉換器（ADC）、數位信號處理器（DSP）等，都可以用延遲鎖定迴路(DLL)來提供一個穩定的系統時脈，讓電路可以達到預期的性能。然而傳統架構的延遲鎖定迴路(DLL)還是有缺點存在，例如鎖定範圍太小，鎖定時間太長，多餘的DC Current...等等，現今又追求著低功耗及穩定的輸出，所以能快速鎖定且低耗能的延遲鎖定迴路，應是一個值得的研究方向。
本論文亦將從快速鎖定(Fast-Locking)、多頻率輸出(Multi-Frequency Outputs)及低功耗(Low power)三項特點同時進行考量已達到改善延遲鎖定迴路(DLL)的目標。我們所提出的延遲鎖定迴路(DLL)架構，利用0.18μm 1P6M CMOS製程設計且操作電壓1.8 V，輸入參考頻率為0.1 GHz而輸出時脈分別為0.2 GHz、0.4 GHz、0.8 GHz及1.6 GHz。

關鍵字

延遲鎖定迴路 ； 多頻率輸出 ； 新型充電幫浦

並列摘要

Due to the frequent use of the current chip, process technology is also more advanced, the clock signals in circuit system has been faster, and non-ideal effects within the chip will produce phase error and delay. This problem can seriously affect the overall system performance. Therefore, the clock synchronization of the digital system circuit becomes more important, especially in high-speed computing systems, the clock skew will be an important factor to determine the performance of the system. Clock synchronization technology usually through the phase-locked loop (PLL) and delay-locked loop (DLL) to eliminate the clock offset, increase the circuit stability, can produce a stable output oscillation frequency, and reduce product costs to increase product competitiveness. The jitter and stability of DLL is better than PLL.
DLL has been widely used in the clock circuits, such as synchronous dynamic RAM (SDRAM), analog-to-digital converter (ADC), digital signal processor (DSP), etc., All of them can use the DLL to provide a stable system clock, so that the circuit can achieve the desired performance. However, there are still some disadvantages existing in traditional DLLs, such as small locking range, long locking time, redundant DC Current, etc. Today's circuits are pursuing low power and stable output. Thus, quickly lock and low power of DLL are a worthy research direction.
In this paper, we will improve the DLL by considering the characteristics of fast-Locking, multi-frequency outputs and low power at the same time. The proposed DLL architecture is based on 0.18μm 1P6M CMOS process with an operating voltage of 1.8 V, input reference frequency is 0.1 GHz and output clocks are 0.2 GHz, 0.4 GHz, 0.8 GHz, and 1.6 GHz.

並列關鍵字

Delay-Locked Loop(DLL) ； Multi-Frequency ； Modified Charge Pump Circuit

參考文獻

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