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  • 學位論文

應用於展頻之全數位式鎖相迴路

An All Digital PLL for Spread Spectrum Clock Generator

指導教授 : 李泰成

摘要


隨著電路技術進步,先進製程有越來越適合數位電路設計的優點。為了要跟上市場需求,小晶片面積與低電源供應器電壓已成為現今的一種趨勢。而在更換製程時,數位電路也有容易重新設計的特性。 全數位式鎖相迴路可以將類比的電荷幫浦與迴路濾波器以數位式的電路來取代,是對於積體電路來說的一大好處。 時脈展頻產生器應用於許多系統中,時脈展頻產生器可以將處生的時脈經由展頻功能,將主要的頻率能量分散,降低其每單位頻寬的輻射功率。 本論文為應用於時脈展頻器之全數位式鎖相迴路。在此使用了兩段式的三角積分調變器去增加使用於展頻功能上調變器的解析度。最後,此晶片是提請台積電的90奈米製程製作。

並列摘要


Recent advances in integrated circuit (IC) technology make fabrication processes very suitable for digital design. In order to satisfy the market requirement, small area and low voltage designs are mandated nowadays. It is easy to redesign with process changes for digital designs. The all-digital phase-locked loop (ADPLL), one of the most recent and significant advancements in the integrated circuits, offers the remarkable advantage of replacing the charge pump and the loop filter with digital loop filter. The spread spectrum clock generator (SSCG) can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth. In this thesis, an all-digital phase-locked loop application for SSCG is implemented in this paper. We use two-stage delta-sigma modulator to improve the resolution of DSM in spread-spectrum clock function. Finally, the experimental ship is fabricated in a TSMC 90nm CMOS process.

參考文獻


[1] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II., vol. 50, no. 11, pp. 815–828, Nov. 2003.
[4] N. D. Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nmCMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1482–1490,Jul. 2005.
[5] “Spread spectrum timing for hard disk drive applications,” http://www.intel.com, Nov. 2000.
[6] M. T. LoBue, “Surveying today’s most popular storage interfaces,” Computer, vol. 35, issue 12, pp. 48-55, Dec. 2002.
[8] Floyd M. Gardner, “Phase lock Techniques,” JOHN WILEY & SONS, INC., 2005

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