全數位展頻時脈產生器

All-Digital Spread Spectrum Clock Generators

林聖祐(Sheng-You Lin)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10306

摘要

無資料

關鍵字

全數位 ； 展頻時脈

並列摘要

In a PC system, the speed of the center process unit (CPU) improves continuously. If the I/O interface is not able to improve simultaneously, the performance of the PC system will be limited. Therefore, high-speed I/O interface are becoming popular. As operating in high data rate, the high-frequency clock causes electromagnetic interference (EMI) which may affect the wireless communication system. Therefore, reduction of unnecessary EMI is a very important issue. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 3Gbps with possible extension to 6Gbps in the near future. In SATA, a spread-spectrum clocking (SSC) technique is specified to reduce the peak EMI emission by spreading the carrier frequency.
In this work, an all-digital spread spectrum clock is proposed for SATA application. The all-digital implemented circuits have the advantage of high portability, small area, high performance in the advanced process, and better integrity in digital system. In the first chip work, a mixed-signal phase/frequency detector is proposed to degrade the quantization noise. The time amplifier is implemented with the phase decision circuit to eliminate the deadzone. The digital controlled oscillator (DCO) resolution enhancement circuit combined with delta-sigma modulator (DSM) is proposed to enhance the resolution of the DCO. With the resolution enhancement circuit, the operation frequency of the DSM is reduced to achieve the same performance. The experimental chip is fabricated in a 0.18um CMOS process. The R.M.S jitter of the output clock is 4ps at 1.5GHz. The achieved EMI reduction is 10.488 dB when SSC turned on.
In the second chip work, a cyclic-Vernier time-to-digital converter (TDC) is proposed to achieve a high resolution TDC. Because of the cyclic structure, the dynamic range is wider and the consumed area is less. The loop filter and the DSM in the modulation controller in this work is one order higher than the first work to achieve better noise performance. The experimental chip is also designed for 1.5GHz SATA specification and is fabricated in a 0.18um CMOS process.

並列關鍵字

All-digital ； Spread spectrum clock generator

參考文獻

[1] W. Cheng, Z. Tan, X. Gao, G. Chang, J. Wen, “High speed serial interface & some key technology research,” Electronic Commerce and Security, Aug. 2008, pp.562-566.

[2] M. T. LoBue, “Surveying today’s most popular storage interfaces,” Computer, vol. 35, pp.48-55, Dec. 2002.

[3] “Spread spectrum timing for hard disk drive applications,” http://www.cypress.com, Nov. 2000.

[6] F. Lin and D. Chen, “Reduction of power supply EMI emission by switching frequency modulation,” in The VPEC Tenth Annual Power Electronics Seminar, Virginia Power Electronics Center, Blacksburg, Virginia, Sep. 20-22, 1992.

[7] D. S. Shen, “A spread spectrum clock generator based on a fractional-N frequency synthesizer,” MS Thesis, National Taiwan University, June 2007.