於0.18微米互補式金氧半製程實現之一伏特兩百億赫茲鎖相迴路設計

Design of a 1-V 20-GHz Phase-Locked Loop in 0.18-um CMOS

方語賢(Yu-Hsien Fang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10203

摘要

本論文之主要研究為可操作於一伏特之兩百億赫茲的鎖相迴路設計，並且提出一個具有交叉耦合電容之電感電容式壓控震盪器。此壓控震盪器利用其與交叉耦合對之輸入寄生電容串聯之結構，使輸出震盪頻率大約提升了約1-GHz之多；此外，此壓控震盪器使用雙端差動、結構對稱且具有高品質因素之電感，並且降低交叉耦合對之等效轉導值，因此達到了相位雜訊在1-MHz位移頻率時為－106 dBc/Hz之效能，而此時之功率消耗為1-mW。
另外一個在鎖相迴路中扮演關鍵性的電路區塊係非除頻器莫屬，面對20-GHz如此高之輸入頻率，第一、二級除頻器乃採用注入鎖定式之除頻器，藉由選擇適當之負載電感，前兩級注入鎖定式除頻器皆操作於合理之中心頻率，但為了能確保除頻器可以正確除頻，因此，可除頻範圍變成高速除頻器之最重要的設計指標，本論文亦提供一個快速且略為精確之可除頻範圍評估，以增加注入鎖定式除頻器之設計效率。
本研究中，在注入鎖定式除頻器之後，使用電流模式邏輯之除頻器當做第三∼六級之除頻器，達到其寬的可除頻範圍之特性，佈局後之模擬結果顯示出可除頻範圍為1.2∼7.3-GHz，因此此除頻器可以在可能發生的PVT偏移之下正常操作。
實際電晶體層與全波電磁分析之共同模擬結果顯示此鎖相迴路鎖定在20.6-GHz，並且在1-MHz之迴路頻寬、參考頻率為160.93-MHz之條件下，達到了－46.6 dBc的參考突波，此時，整個鎖相迴路之功率消耗為18.5-mW。

關鍵字

鎖相迴路 ； 壓控震盪器 ； 米勒除頻器 ； 除頻器 ； 參考突波 ； 低電壓

並列摘要

In this work, a 20-GHz PLL with a 1-V supply is designed, where a pair of cross-coupled capacitors, Cf, is proposed and added to the LC-VCO. The two capacitors are inserted between the output and the gate of cross-coupled pair in the LC-VCO, and therefore lower the equivalent capacitance at output while looking into the series connection of Cf and the gate capacitance of cross-coupled pair. The LC-VCO uses this configuration, and therefore makes the output oscillation frequency raised by 1.0 GHz approximately. Besides, the LC-VCO employing a differential, geometrically symmetrical with high Q inductor and lowering the transconductance of cross-coupled pair accomplishes a phase noise of －106-dBc/Hz at 1-MHz offset with a minimum power of 1-mW.
Frequency divider plays an essential role in a PLL system. In divider chain, the injection-locked frequency dividers are employed in the first and the second stage dividers. By selecting an adequate load inductor, the first and the second injection-locked frequency dividers operate at desired center frequency accordingly. Whereas, in order to ensure the frequency dividers can functionally work, a parameter, locking range, therefore becomes the most important design target especially for high-speed frequency dividers applications. This thesis provides a rapid and roughly accurate estimation of divider locking range, so as to increase design efficiency in injection-locked frequency dividers.
In the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after two-cascaded-stage injection-locked frequency dividers, arriving at a wide-locking-range characteristic. According to the post-layout simulations of the third to the seventh stages frequency dividers, they achieve a 1.2 to 7.3-GHz locking range wide. This result demonstrates the third to seventh stage frequency dividers can correctly operate under possible PVT variations.
The transistor-level and 2.5-D EM co-simulation results of the PLL reveal that the PLL is locked at 20.6 GHz, and it achieves a magnitude of －46.6-dBc reference spurs with a 1-MHz loop bandwidth and a 160.93-MHz reference frequency, while consuming 18.5 mW from a 1-V supply.

並列關鍵字

Phase-locked loop (PLL) ； voltage-controlled oscillator (VCO) ； Miller divider ； frequency divider ； reference spurs ； low-voltage

參考文獻

[2] A. Babakhani, X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri, “A 77-GHz 4-element phased array receiver with on-chip dipole antennas in silicon,” in IEEE ISSCC 2006 Dig. Tech. Papers, pp. 180-181, Feb. 2006.

[4] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.

[5] B. D. Muer and M. Steyaert, CMOS Fractional-N Synthesizers Design for High Spectral Purity and Monolithic Integration, Kluwer Academic Publishers, 2003.

[6] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” IEEE ISCAS, vol. 2, pp. 545-548, May 1999.

[7] T.-H. Lin, Lecture notes: Sensor Interface IC Design, NTU.