在多路徑頻率選擇性通道下使用聯合載波同步與通道等化演算法之OFDM收發機系統設計與其CORDIC-Based超大型積體電路架構設計

本論文，主要是考量在多重路徑頻率選擇性通道(multipath frequency-selective fading channel)下，探討正交分頻多工(orthogonal frequency-division multiplexing, OFDM)基頻收發機的系統設計與驗證。另外，針對OFDM系統在追蹤階段(tracking stage)，提出載波同步與通道等化之聯合演算法。此聯合演算法是根據最小均方誤差(minimum mean-square-error, MMSE)準則，定出其單一成本函數(cost function)，可同時最小化子通道上的均方誤差，進而減弱載波頻率抖動(jitter)。基本上，聯合演算法包含了一個雙迴路(dual-loop)的載波同步與一個增益(gain)等化回路。此雙迴路是由內部(inner)迴路與外部(outer)迴路組成的架構。此外，針對硬體實現所造成迴路延遲(loop-delay)，進而引起雙迴路的相關穩定度問題與迴路抖動對系統效能(performance)的影響，在此論文中都做了詳盡的探討與分析。針對AWGN與頻率選擇性通道的情況下，透過系統模擬驗證系統的分析，其結果可以顯示出聯合演算法不僅可以準確的估測與補償載波頻率偏移和通道等化，且具有成本效益的特色。在考量相關的演算法比較下，聯合演算法在乘法與加法運算上，可分別節省18.8%/57.2%與12.4%/49.1%的算術運算功率(computational power)。考量聯合演算法的算術運算特性，針對OFDM基頻接收機，提出以CORDIC-based的超大型積體電架構設計，進而降低整個接收機的硬體複雜度。聯合演算法中其算術運算包含座標旋轉(coordinate rotation)、反正切(arctangent)、平方相加(square & addition)與平方根(square-root)、乘法與除法運算等。這些算術運算可以很簡單的透過控制單元，在不同的時間將CORDIC設定成相對應的組態，執行上述各個算術運算。此外，為了要得到合理的硬體設計，根據系統可接受的SNR損失下，針對OFDM系統的接收信號路徑作其定點分析。以Altera Stratix II EP2S180建立一個OFDM基頻接收機的FPGA原型機，驗證其相關的系統規格。在IEEE 802.11a且其載波偏移頻率(carrier frequency offset, CFO)為-232.2 KHz，64-QAM非編碼(uncoded)的最大傳送資料量72 Mbps下，其誤差向量振幅(error vector magnitude, EVM)的量測結果為-31.0 dB，且符合系統要求(<-25 dB)。最後，以TSMC 0.18um 1P6M CMOS製程，完成此CORDIC-based超大型積體電路架構設計的OFDM基頻接收機的實體佈局。其晶片與核心面積分別為2.1 mm^2與1.2 mm^2。根據佈局後模擬(Post-layout simulation)的結果與Prime Time的估計，其總消耗功率在核心(core)電壓1.8 V、晶片輸入/輸出埠(I/O pad)電壓1.5 V與系統時脈40MHz的情況下為51 mW，其晶片核心消耗功率為33.2 mW。

關鍵字

正交分頻多工；載波同步；通道等化；坐標旋轉數位計算器；聯合演算法

並列摘要

In this dissertation, both design and evaluation of an OFDM baseband transceiver over the multipath frequency-selective fading channel are presented. Besides, a joint carrier synchronization synchronization and channel equalization algorithm is proposed for the OFDM baseband receiver in the tracking stage. Based on the minimum mean-square-error (MMSE) criterion, the cost function of the joint algorithm is addressed to concurrently minimize the MSE on each subchannel and to further lower the carrier frequency jitter. Basically, the carrier synchronization scheme with multirate processing is a dual-loop structure, which is composed of outer and inner loops. In particular, the closed-loop stability of the carrier synchronization loop is explored for the loop-delay induced by the hardware implementation. Many simulations are done for the additive white Gaussian noise (AWGN) and the multipath frequency-selective fading channels to show that the joint algorithm not only accurately estimates and compensates the carrier frequency offset (CFO) and the channel impairment but also provides the cost-effective feature. Furthermore, the joint algorithm can save 18.8%/57.2% and 12.4%/49.1% of computational power in multiplication and addition operations compared with the considered algorithms. Considering the unique features of the joint algorithm, the COordinate Rotation DIgital Computer (CORDIC)-based VLSI architecture of OFDM baseband receiver is presented to further reduce the hardware complexity. Several arithmetic functions including coordicate rotation, arctangent, square & addition, square-root and multiplication and division, can be easily realized by configuring the rotation types and modes of CORDIC at different time slot. In order to obtain the reasonable hardware design, the fixed-point analyses of the received signal path for the OFDM baseband receiver are derived based on a restrictive SNR degradation. The FPGA prototyping of OFDM baseband receiver is evaluated by Altera Stratix II EP2S180 (F1020 C3) at 40 MHz system clock. In addition, the measurement of the error vector magnitude (EVM) for 64-QAM is -31.0 dB, which meets the required EVM (<-25 dB) for IEEE 802.11a system, under the maximum uncoded data rate 72 Mbps. Finally, the physical layout of the proposed CORDIC-based VLSI architecture for OFDM baseband received is fulfilled with TSMC 0.18um 1P6M CMOS technology. The chip area is 2.1 mm^2 and the core area is 1.2 mm^2. Besides, the total power consumption, estimated by Prime Time, is 51 mW @1.8V (core) and 3.3 V (pad) with 40 MHz system clock, and thus, the core power is 33.2 mW.

並列關鍵字

OFDM ； Carrier Synchronization ； Channel Equalization ； CORDIC ； Joint Algorithm

參考文獻

[2] P. H. Moose,"A Technique for Orthogonal Frequency Division Multiplexing Frequency Offset Correction,"

[3] T. Pollet, M. V. Bladel and M. Moeneclaey, "BER Sensitivity of OFDM Systems to Carrier Offset and Wiener Phase Noise," IEEE Trans. on Comm., vol. 43, no. 2/3/3, pp.

191-193, Feb./Mar./Apr. 1995.

[4]M. Luise and R. Reggiannini, "Carrier Frequency Acquisition and Tracking for OFDM Systems," IEEE Trans. on Comm., vol. 44, no. 11, pp. 1590-1598, Nov. 1996.

[5] M. Speth, S. A. Fechtel, G. Fock and H. Meyer, "Optimum Receiver Design for Broad-Band Systems Using OFDM-Part I," IEEE Trans. on Comm., vol. 47, no. 11, pp. 1668-1677, Nov. 1999.

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在多路徑頻率選擇性通道下使用聯合載波同步與通道等化演算法之OFDM收發機系統設計與其CORDIC-Based超大型積體電路架構設計

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