應用在 100Gb/s 乙太網路之1/2.5速率比資料與時脈回復電路

A 1/2.5-Rate Clock and Data Recovery Circuit for 100Gb/s Ethernet in 40 nm Technology

鄭家凱(Chia-Kai Cheng)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201602430

摘要

2010 年六月，IEEE P802.3ba 被正式提出，定義了40GbE 與100GbE 的規範，目的是將IEEE 802.3 的協定延伸至40Gbps 與100Gbps 的操作速度，並同時符合現行協定與傳輸距離的要求。IEEE P802.3ba 定義之100GbE 將單一通道100Gbps的光信號以波長分割多工轉換(Wavelength Division Multiplexing）分割成四條25Gbps 的子通道，以達到高速通訊傳輸的目的。
在光通信系統中，由於傳輸通道的成本相當昂貴，通常希望能在單一通道內能傳輸更高頻的資料，以減少傳輸通道的成本。在100GbE 的接收器系統，需要將四通道25Gbps 的高速信號解調至十通道10Gbps 的低速信號，此種2:5 的資料比率比起傳統2 次方倍率的解調器（e.g.,1:16 DEMUXing）設計上更為複雜，並且會有較大面積與功率消耗 ，此論文提出一1⁄2.5資料速率比的資料與時脈回復電路（Clock & Data Recovery Circuit, CDR）可以不必經過2:5 解調器便將資料分離成低頻信號，以減少硬體資源的消耗，此CDR 使用TSMC 40 奈米製程，在1-V 的電源供應下只消耗51.5mW/Channel。

關鍵字

100Gb/s乙太網路 ； 時脈與資料回復電路

並列摘要

In June, 2010, IEEE P802.3ba is generated officially. It defines the specification of 40GbE and 100GbE. The purpose is to extend the operation speed of the IEEE 802.3 agreement to 40Gbps and 100Gbps, and at the same time it also accords the current agreement and the demand of the transmission distance. At the definition of IEEE P802.3ba, the 100GbE is used four channels of 25Gbps output of with wavelength division multiplexing to achieve the purpose of high speed transmission.
At optical communication systems, since the cost of the transmission line channel is very expensive, in order to reduce the cost, we usually hope we can transmit higher frequency data in single channel. At the 100GbE receiver system, we need to deserialize four channel 25Gbps signal into ten channel 10Gbps. Unlike the conventional power of 2 deserializer, the 2:5 data ratio would suffer from more complicate design, and consume more area and have more power dissipation. A 1/2.5-rate clock and data recovery (CDR) circuit is proposed in this thesis. We can deserialize the signal without 2:5 deserializer to reduce the hardware resource. This CDR is implemented in TSMC 40nm CMOS technology. At 1V power supply, it only consumes 51.5mW/Channel.

並列關鍵字

100Gb/s Ethernet ； Clock and data recovery circuit

參考文獻

[1] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1st Ed., McGraw-Hill, 2001.

[4] B. Razavi, “Design of Integrated Circuits for Optical Communications,” 1st Ed., Mc-Graw Hill, 2003.

[5] S. Galal and B. Razavi, “40-Gb/s Amplifier and ESD Protection Circuit in 0.18-μm CMOS Technology” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389-2396, Dec. 2004

[8] R. Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, and H. Siedhoff, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with an Analog Phase Interpolator,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 736-743, Mar. 2005

[9] C. Kromer, G. Sialm, C. Menolfi, M. Schmatz, F. Ellinger and H. Jäckel, “A 25Gb/s CDR in 90-nm CMOS for High-Density Interconnects,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2921–2929, Dec. 2006.