操作在1.2V電壓使用延伸線性控制範圍VCO的2.5Gbps時脈資料回復電路

1.2V 2.5Gbps Clock and Data Recovery with Extended Linear Control Range VCO

陳惠育(Hui-Yu Chen)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2008年)

https://doi.org/10.6837/NCNU.2008.00191

摘要

時脈資料回復電路（CDR）在乙太網路、光纖網路以及晶片內部的串列資料傳輸中是一個很重要的元件。而高速度、低功率的時脈資料回復電路一直有很廣泛的使用需求。本論文將介紹時脈資料回復電路的架構與設計考量，設計與實現一操作在低電壓的高速時脈資料回復電路，並且使用Matlab Simulink建立模型分析電路穩定度以及電路可行性。
本論文使用TSMC 0.18um 1P6M CMOS 製程，實現一個電源電壓操作在1.2V的2.5Gbps時脈資料回復電路。使用1.25 GHz電壓控制震盪器（VCO）實現半速率時脈資料回復電路，論文中提出一個改良的延遲單元，使VCO的線性控制電壓範圍延伸為0~1.2V以符合低電壓的操作，也改善VCO的頻率-電壓特性曲線的線性度及降低電壓控制震盪器的增益。壓控震盪器的模擬結果得到頻率範圍從0.76GHz到1.5GHz，抖動的峰對峰值為30 ps，在中心頻率1MHz附近的相位雜訊為-100.7dBc/Hz，VCO電路的功率消耗為1.8mW，包含Buffer的VCO功率消耗為3.21mW；在電源電壓為1.2伏特時，時脈資料回復電路的模擬結果得到消耗功率為49.5mW，抖動175ps；半速率相位偵測器的消耗功率為12.7 mW，推動晶片外負載的緩衝器的消耗功率為33 mW。為了方便測試，晶片中還包含了一個2.5GHz的鎖相迴路和亂數資料產生器，整個晶片面積為920um* 920um，其中CDR的面積為322.4um* 403.3um。

關鍵字

半速率 ； 時脈資料回復電路 ； 電壓控制振盪器

並列摘要

Clock and data recovery (CDR) circuit is a key component used in Ethernet, optical network and serial link. High-speed and low-power CDR circuits find their applications in a variety of communication systems. The thesis introduces the architectures and some design issues of clock and data recovery circuits. A low voltage and high speed CDR is then designed and implemented. Behavior model built by using Matlab Simulink is used to simulate and analyze the function and stability of the CDR.
A 1.2V 2.5Gbps CDR circuit has been implemented in TSMC 0.18um 1P6M CMOS process. A half-rate CDR circuit using 1.25GHz VCO is presented. The VCO uses a modified delay cell to extend the linear control range to 0~1.2V for low voltage operation. The linearity and gain of the VCO transfer characteristics are much improved. The modified VCO works at a tuning range from 0.76 GHz to 1.5GHz, and its peak-to-peak jitter at 1.25 GHz is 30ps. The phase noise is -100.7dBc /Hz at 1MHz offset from a 1.25GHz center frequency. The power consumption of the core circuit is 1.8mW, with buffer is 3.21mW. The clock and data recovery circuit consumed 49.5mW at 1.2V power supply, and its jitter is 175ps. The power consumption of the half-rate phase detector is 12.7 mW. The circuit buffers consumed 33mW. For testing purpose a 2.5GHz PLL and a 215-1 PRBS generator are included in the chip. The whole chip area is 920um*920um. The CDR circuit area is 322.4um*403.3um.

並列關鍵字

Half Rate ； clock and data recovery ； voltage control oscillator

參考文獻

參考文獻

[1] Behzad Razavi, “Design of high-speed circuits for optical communication systems,” IEEE Custom Integrated Circuits Conference, pp. 315-322, May. 2001.

[2] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill,2001.

[3] K. Y. Chang, Design of a CMOS Asymmetric Serial Link, Ph.D. Dissertation, Stanford University, August 1999.

[4] The Long-Haul Network