低耗正交壓控震盪器於0.6-V和2.4GHz鎖相迴路的設計與分析

A Quadrature VCO with Low Power 0.6-V and 2.4-GHz Phase-Lock Loop

陳昕怡(Hsin-Yi Chen)

指導教授 ： 陳淳杰

中原大學/工學院/電子工程研究所/碩士(2013年)

https://doi.org/10.6840/CYCU.2013.00093

摘要

由於正交壓控震盪器(QVCO)建立在反相耦合上，所以使用被動的MOSFET可以使輸出的正交相位有較低的功率消耗。在鎖相迴路當中，壓控震盪器是功率消耗最高的部分之一。為了降低功率消耗，本研究使用正交壓控震盪器來達成低功率；低電壓的目標。研究採用台積電0.18-μm ，1P6M RFCMOS製成，佈局面積為1.19 mm×1.15 mm。在供應電壓為0.6-V，功率消耗為11.912 mW，相位雜訊在偏移率1 MHz為-102.17 dBc/Hz。

關鍵字

LC-壓控震盪器 ； 正交壓控震盪器 ； 鎖相迴路 ； 低電壓 ； 低功耗

並列摘要

The performance of Quadrature Voltage-Controlled Oscillator (QVCO) depends heavily on the antiphase coupling. To employ a passive mode MOSFETs, quadrature phase output can bring out the lowest power consumption. The parallel and the cascode QVCO which with active coupling are used for applying category RF frequencies. Nevertheless, as a result of operations of active coupling transistors, extra bias current or voltage range is required. For so much as the passive coupling, in order to an enlarge chip area, on-chip transformers are typically exploited. In the Phase Lock Loop (PLL) circuit, VCO is the most power consumption block. Accroding to the reason, in this study the QVCO is used which can reach low-power and low-voltage. This QVCO design was implemented in TSMC 0.18 μm 1P6M RFCMOS technology, and the active area is 1.19 mm×1.15 mm. The power consumption is 11.912 mW from 0.6 V supply, and phase noise at 1 MHz offset is -102.17 dBc/Hz. By applying a 15 MHz reference frequency, the QVCO in the PLL turn out 2.4 GHz. From the outputs waveform, the phase error is about 2.5˚.

並列關鍵字

LC-VCO ； Quadrature Voltage controlled Oscillator ； Phase-Lock loop ； low-power ； low-voltage

參考文獻

[1] Chung-Ting Lu, Hsieh-Hung Hsieh, Liang-Hung Lu, “A low-power quadrature VCO and its application to a 0.6-V 2.4 GHz PLL”, IEEE　Transations on Circuits and Systems, vol. 57, no. 4, April 2010.

[5] A. Ravil, K. Soumyanath, L. R. Carley, and R. Bishop, “An intrgrated 10/5 GHz injection-locked quadrature LC VCO in a 0.18 um digital CMOS process,” in Proc. IEEE Eur. Solid-State Circuits Conf., pp.543-546, sep. 2002,.

[6] H.-H. Hsieh, C.-T. Lu, and L.-H. Lu, “A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18- um CMOS,” in IEEE Symp. VLSI Circuits Dig. Techn. Papers, pp. 164–165, Jun. 2007.

[7] W. Rhee, “Design of high performance CMOS charge pumps in phaselocked loops,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 2, pp. 545–548, May 1999.

[8] W. Rhee, “Design of high-performance CMOS charge pumps in phaselocked loops,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp. 545–548, 1999.