應用於腦波偵測之類比前端電路設計以及開迴路以壓控振盪器為主之類比數位轉換器

在未來IoT產業的蓬勃發展是可以預期的情況下，對於外界訊號的感測將會無所不在，現今像是汽車產業積極發展各項”智慧汽車”，或是各大軟體公司推出的”智慧居家管理”背後除了是5G研究高度發展之外，也需要各式各樣高精度的感測元件做為輔助，把環境中的類比訊號轉成數位的方法做處理，所以一個高精度，低面積(低成本)，低功耗的感測介面是一個大趨勢。本論文實作了兩個電路。第一個作品實作一個用於腦波偵測的低功耗與低雜訊類比前端電路。此晶片實作於台積電180奈米製程。此前端電路包括了一個低雜訊儀表放大器與可編程式儀表放大器，這兩個儀表放大器皆選用電容耦合式儀表放大器來達成低功耗的訴求。最後達到整體功耗26.41微瓦特(單一通道)，並且在0.5到400赫茲的頻寬下得到積分雜訊為1.43微伏特(方均根)，而雜訊效率比(NEF)則達到7.8。第二顆晶片實作了高度數位實現開迴路壓控震盪器為主之類比數位轉換器。此電路實作於台積電180奈米製程，本電路把壓控震盪器拆分成跨導加上電流控制振盪器的結構，藉由設計跨導電路，將輸入範圍大幅度的提升，增加本電路的實用性。此外，我們使用數位截波器來消除整個系統的低頻雜訊，同時只用一個壓控震盪器來取代差動壓控震盪器，避免兩個差動壓控震盪器的不匹配問題。在類比數位轉換器的輸出端我們加入非線性消除的演算法，進一步提升整體的線性度。此晶片核心面積僅0.26平方毫米，功耗為0.65 W(數位電路以及跨導電路使用1.2 V電源，其餘類比電路使用1.8 V電源)。輸入範圍為1.52 Vpp，線性度方面經過量測在頻寬為100 kHz下達到9.3有效位元數，在品質因素方面達到FoMs = 140 dB及FoMw = 5.1 pJ/conv。

關鍵字

低功率；低雜訊；類比前端電路；壓控震盪器；類比數位轉換器；數位截波器；非線性消除

並列摘要

In this dissertation, two circuits are presented. The first one realizes a low-power and low-noise analog front-end circuit for EEG application. It is fabricated in TSMC 180-nm process. The analog front-end (AFE) includes a low noise instrumentation amplifier (LNA) followed by a programmable gain amplifier (PGA) to further increase the gain. Both LNA and PGA employ capacitively-coupled IA (CCIA) topology to achieve good power efficiency. This chip uses the architecture without the chopper technique and achieves total power consumption of 26.41 W per channel. The integrated noise from 0.5 to 400 Hz is 1.43 Vrms. The noise efficiency factor (NEF) is 7.8. The second work implements a highly digital open-loop VCO-based ADC with a chopper for sensor applications. It is fabricated in TSMC 180-nm process. This circuit divides the voltage-controlled oscillator into a structure of transconductance and a current-controlled oscillator. By designing the transconductance circuit, the input range is greatly improved and the practicability of the circuit is increased. This work proposes a quasi-chopping operation that suppresses low-frequency noise throughout the system. At the output of the analog-to-digital converter, we add a nonlinearity cancelation (NLC) algorithm to further improve the overall linearity. The core area of the circuit is 0.26 mm2. The power consumption is 0.65 mW under 1.2 V supply for digital circuit and Gm-stage where 1.8 V supply for other analog circuits. With the input range being 1.52 Vpp, the ENOB is 9.3 with a bandwidth of 100 kHz. The figure of merits FoMs is 140 dB and FoMw is 5.1 pJ/conv.

並列關鍵字

Low-Power ； Low-Noise ； Analog Front-End (AFE) ； Voltage-Controlled Oscillator ； Analog to Digital Converter (ADC) ； Quasi-Chopping ； Nonlinear Cancelation (NLC)

參考文獻

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