應用於寬頻序列分工多重擷取系統直接降頻接收機的直流電壓偏差消除技巧

人與人之間的行動通訊發展的相當快，而新的無線通訊技術和協定也很快的被熱心的人們採用。因為RF技術的進步，數位電路的發展，行動通訊技術工業正在以倍數的成長。而行動通訊所需要的通訊端硬體，也因為VLSI技術的改善與進步，變的更小，更便宜，攜帶更方便，也更可靠。對於行動通訊的接收機設計中，直接降頻接收機是一個很重要的架構。因為比較有利於整合於晶片當中。但是直接降頻接收機有許多的問題，直流電壓偏差是其中較嚴重的一項。它會造成整個接收機的敏感度降低，而且降低整個基頻電路的動態區域。許多直流電壓偏差的消除技巧已經研究出來，可以增加接收機的效能，並提供足夠大的動態區域。在本論文，我們描述一個可以應用在寬頻序列分工多重擷取系統的直流電壓偏差消除技巧。系統模擬結果顯示，此直流電壓偏差消除電路的截止頻率必須在 10 kHz 以下。另外，一個通道選擇濾波器也被整合在同一個的晶片當中。此直流電壓消除電路是以頻率相關負電阻為基礎，此負載可作為一個直流回授迴路，校正在輸入端的偏差電壓。模擬結果顯示，它可以只需要普通伺服回路四分之ㄧ的電容即可以提供足夠的衰減度和截止頻率。此晶片只使用1.8 V的電壓源，消耗8 mW，並使用0.18毫微米CMOS製程來設計此晶片。

關鍵字

基頻電路；直流偏壓偏差消除；直接降頻接收機

並列摘要

The ability to communicate with people on the move has evolved remarkably, and new wireless communications methods have been enthusiastically adopted by people throughout the world. The mobile radio communications industry has grown by orders of magnitude because of the digital and RF circuit fabrication improvements, new large-scale circuit integration and other miniaturization technologies which make portable radio equipment smaller, cheaper and more reliable. For mobile receiver design, direct-conversion receivers are most important architecture for monolithic integration. But, DC offsets in direct-conversion receivers is one of the critical problems. Lots of the offset cancellation techniques are developed to enhance the receiver performance, and provide large dynamic range for the baseband circuit. In this thesis, we describe the implementation and measurement results of offset cancellation architecture for WCDMA mobile system. A system simulation indicates the offset cancellation must provide a 10-kHz corner frequency. A channel selection filter is also integrated in the chip to provide 40-dB adjacent channel selectivity. The offset cancellation is composed of a FDNR based load to provide a DC feedback loop to correct the offset voltage. Simulation results show that only quarters of capacitors can be used to provide the same corner frequency and attenuation compared with the conventional servo loop. The chip consumes 8 mW from a 1.8-V supply and is fabricated in a 0.18-μm CMOS technology.

並列關鍵字

baseband circuit ； DC offset cancellation ； Direct conversion receiver

參考文獻

[1] Behzad Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE Transactions on Circuits and Systems, vol. 44, pp. 428-435, Jun. 1997.

[3] Aarno Parssinen, Jarkko Jussila Jussi Ryynanen, Lauri Sumanen, and Kari A.I.Halonen, “A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Applications”, IEEE Journal of Solid State Circuit, vol. 34, pp. 1893-1902, Dec. 1999.

[4] US patent, No. 6115593. “Elimination of D.C. Offset and Spurious AM Suppression in a Direct Conversion Receiver”.

[5] US patent, No. US5749051. “Compensation for Second Order Intermodulation in a Homodyne Receiver”.

[7] Rolf Schaumann and Mac E. Van Valkenburg, “Design of Analog Filters”, Oxford, 2001.

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應用於寬頻序列分工多重擷取系統直接降頻接收機的直流電壓偏差消除技巧

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