一個超低功率消耗的類比數位轉換器

An Ultra-low Power Analog to Digital Converter

戴宏彥(Hung-Yen Tai)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01164

摘要

一個10位元解析度每秒80萬次取樣的循序漸近式類比至數位轉換器(SAR ADC)實現在TSMC的90nm製程上，此 SAR ADC 可以在低電壓下操作的很好。在使用分離式電容切換技巧上面，功率消耗僅為2.88微瓦，換算成FoM為10.2fJ/c.s.。
因為 SAR ADC 的功率消耗約為0.5*C*V2*f，所以可以藉由減少電晶體本身的電容與降低工作電壓來節省所需的功率消耗。此晶片使用先進製程且供應電壓為0.5V，並使用了電荷升壓技巧讓取樣開關能完全的開啟或關閉，加上為了讓比較器的輸入差動對能使用NMOS，採用了電壓位準平移的方式來達成此目的。此晶片在量測中得到SFDR為66.19dB，SNDR為52.72dB且換算成ENOB為8.47bit。整個晶片所佔的面積為0.49mm2，而主動電路只有0.038mm2。

關鍵字

循序漸進 ； 類比至數位轉換器 ； 低功率 ； 低電壓

並列摘要

A 10-bit 800KS/s SAR ADC (Successive Approximation Register Analog to Digital Converter) is demonstrated in a standard TSMC 90nm process. This SAR ADC can operate well in low supply voltage. By using split-capacitor technique, its power consumption is only 2.88uW. The FoM (Power / 2ENOB / Fs) of this chip is 10.2fJ / conversion-step.
Since the power of SAR ADC approximates to 0.5*C*V2*f, it can save power by reducing the MOS capacitor and lowering the supply voltage. This chip is implemented in advanced process and its supply voltage is 0.5V. In such a low voltage, it uses a charge pump to fully turn on or turn off the sampling switch. For the purpose of using NMOS input pair comparator, the level-shift method is adopted. The measurement results show that the SFDR is 66.19dB, the SNDR is 52.72dB, and the ENOB is 8.47-bit. The chip size occupies 0.49 mm2, and the active area is only 0.038 mm2.

並列關鍵字

SAR ； ADC ； Low Power ； Low Voltage

參考文獻

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