- 學位論文
低功耗雙基底對數型類比數位轉換器
A Low Power Double-base Logarithmic Analog to Digital Converter
摘要
對數型數位類比轉換器可偵測大範圍變動之訊號，亦可簡化後方的數位運算。本論文提出一低功率消耗的電路實現，相較於傳統線性型逐次逼近暫存器式類比數位轉換器[16]，可節省99.6%的切換能量；此對數型類比數位轉換器僅須一個參考電壓、且具有雙基底轉換功能之對數型類比數位轉換器，我們並基於此架構設計出應用於偵測光或電訊號平均強度之接收訊號強度指標電路。 晶片實作分成兩個版本：8位元1.25MS/s雙基底對數型類比數位轉換器、及8位元625KS/s光或電訊號平均強度偵測電路。兩者的類比電路供給電壓是1.65V和3.3V，數位電路是0.9V，皆使用0.18um互補式金氧半場效電晶體製程，晶片面積均是 。 於第四章介紹之第一個版本的動態範圍48dB，其直流DNL峰值是0.55 -LSB、INL峰值是0.96-LSB，功率消耗240uW，FOM (pJ/conv. step)約為0.5。 於第五章介紹之第二個版本的動態範圍96dB，其直流DNL峰值是0.75 -LSB、INL峰值是1- LSB，功率消耗320uW，FOM (pJ/conv. step)約為2.1。
並列摘要
Logarithmic analog to digital converter can detect signal changes with wide dynamic range, and also benefits digital computation. A low power logarithmic analog to digital converter that needs only one signal reference voltage and has double bases is presented in this thesis. Based on this architecture, we then design the circuit as a receive signal strength indicator (RSSI) for average optical or electronic signal strength detection. Two versions chips are implemented：An 8-bit 1.25MS/s double -base logarithmic analog to digital converter, and an 8-bit 625KS/s circuit for average optical/electronic signal strength detection. Both of them have dc supplies of 1.65V or 3.3V for analog circuit, and 0.9V for digital circuit. The chips are fabricated in 0.18um CMOS process in the same area of . The first version in chapter 4 has 48dB dynamic range, achieving 0.55-LSB peak DNL and 0.96-LSB peak INL. It consumes 240uW and the FOM (pJ/conv. step) is 0.5. The second version in chapter 5 has 96dB dynamic range, achieving 0.75-LSB peak DNL and 1-LSB peak INL. It consumes 320uW and the FOM (pJ/conv. step) is 2.1.
參考文獻
延伸閱讀
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