低雜訊雙通道管線式類比數位轉換器

Low Noise Dual Channel Pipelined ADC

江文男(Wen-Nan Chiang)

指導教授 ： 宋國明

國立臺北科技大學/電資學院/電資碩士班/碩士(2009年)

摘要

隨著可攜式電腦、通訊、消費性電子產品的廣泛成長，在顯示器與無線通訊應用上，對於低功率、高速度的類比訊號轉換成數位訊號的介面電路有著不可或缺的需求。對類比數位轉換器而言，為求高解析度及高速的轉換率，管線式類比數位轉換器 (Pipelined ADC)為目前較佳的選擇。本論文主要是採用九級管線式類比數位轉換器架構，前八級每一級為1.5 bit及後一級2 bit組成10 bit管線式類比數位轉換器;為實踐低功率、高速度、高解析度的要求，每一級採用雙通道1.5 bit Flash ADC，是由於Flash ADC具有高速操作的優點，而雙通道的設計在於利用操作在系統時脈正負週期以達到省能與雜訊的消除。
整篇論文簡單的描述導管式類比數位轉換器基本原理，以及導管式類比數位轉換器從設計到電路實現。在系統電路的實現上，我們採用TSMC 0.18μm的互補式金氧半導體製程參數進行模擬與製作晶片。其核心面積約為 0.6 1.47 mm2，消耗功率約為21.6 mW，若以 5 MHz 取樣頻率、輸入頻率44.1 kHz的弦波進行測試，可得到41.5 dB的訊號雜訊失真比，及有效位元數為 6.6 位元。

關鍵字

管線式類比數位轉換器 ； Flash ADC ； 雙通道

並列摘要

Due to the portable computer, communication, and consuming electronic grew up extensively. In the application of the display and wireless communication ,as to the low power, and high speed, that the interface circuit of analog to digit converter has indispensable demands. The pipelined analog to digital converter is a better choice at present which has high speed conversion ratio and high resolution for the analog to digital converter.
The main structure used the 9 stages pipelined ADC. In this thesis the 10 bits pipelined ADC is composed of the first 8 stages which each stage 1.5 bit and the last stage that has 2 bit. In order to get low power, high speed, and high resolution , each stage used the dual channel 1.5bit Flash ADC. Because of the 1.5bit flash ADC have high-speed operation advantage and the dual channel structure can decrease the power consumption and reduce the noise when it work in positive and negative duty cycle respectively. We descript the basic principle of pipelined analog to digital converter and realize from designing to the circuit. We adopt the TSMC 0.18 μm CMOS technology to simulation the circuit of system and implement it. the core area is about 0.6 1.47 mm2, and the power consumption is about 21.6mW. If the bandwidth of the input signal is 44.1 kHz sine wave, we obtain the 41.5 dB peak signal to noise and distortion ratio, and simulation results ENOB=6.6 bits.

並列關鍵字

Pipeline ADC ； Flash ADC ； Dual channel

參考文獻

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