高速之逐漸趨近式類比數位轉換器設計

Design of a High Speed SAR Analog-to-Digital Converter

蔣宗霖(Chung-Lin Chiang)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201803097

摘要

類比數位轉換器在現今的SoC系統中扮演關鍵的元件，因為其連接了真實世界的類比訊號與數位訊號處理器。隨著近年來攜帶式裝置迅速發展，高速低功耗的類比數位轉換器需求也隨之劇增。此篇論文提出了一種類比數位轉換器之設計，達到高速、低功率消耗等設計目標。本論文中首先提出一個單一通道八位元、十六億赫茲取樣率的管線式連續漸進暫存類比數位轉換器。轉換器架構上分為三級，使用兩種被動式餘值轉移的技巧來節省功耗，提出的架構實現於四十奈米製程中，在1.1伏特供應電壓下消耗6.9毫瓦。信噪失真比(SNDR)為38.48分貝，品質因數(FoM)是62.8 fJ/conversion-step，核心電路占據0.032毫米平方面積。

關鍵字

管線式連續漸進暫存類比數位轉換器 ； 被動式餘值轉移

並列摘要

Analog-to-digital converter (ADC) has been recognized as one of the crucial building blocks in the modern SoC system because it provides the link between the real-world analog information and the digital signal processors (DSPs). The demand on high-speed and low-power ADCs has increased as many portable applications grow rapidly in recent years. In this dissertation, an 8-b ADC is presented to achieve high-speed and low-power design.This dissertation demonstrates an 8-b, 1.6-GS/s pipelined-SAR ADC. The proposed ADC is partitioned into 3 stages with two kinds of passive residue transfer technique for power saving. The prototype, fabricated in a 40-nm CMOS technology, consumes 6.9 mW from a 1.1-V supply and achieves an SNDR of 38.8dB near Nyquist-rate. The figure of merit (FoM) is 62.8 fJ/conversion-step and the active area is 0.032 mm2.

並列關鍵字

Pipelined-SAR ADC ； Passive residue transfer technique

參考文獻

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