全數位校正的高解析度連續漸進式類比至數位轉換器

All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter

江豐任(Feng-Jen Chiang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201900262

摘要

類比至數位轉換器可以將自然界類比訊號轉換成數位訊號提供數位處理器做分析。本論文提出一個操作在0.9伏特電壓每秒一百萬次取樣的十四位元連續漸進式類比至數位轉換器，實現於40奈米製程。
本電路使用次區間電路架構，配合偵測與迴避切換及同步切換來降低電容陣列的切換能量消耗，並使用追蹤切換的平均技巧提升對比較器雜訊的抵抗性及能量效率。由於縮小電容能減少電容切換能量，為了解決嚴重的電容誤差，還有偵測與迴避切換的架構限制，使用分離式權重補償技巧可以完美克服權重補償的瓶頸。且次區間電路架構存在著比較器之間的電壓平移誤差，背景平移誤差校正能追蹤誤差量，並回傳至類比電路做校正來降低平移誤差造成的影響和次電路比較器的能量消耗。
本文提出的類比至數位轉換器在每秒一百萬次取樣速度下，功率消耗為8.38瓦特。校正後，差動非線性和積分非線性分別為0.51/-0.54和1.34/-1.31最低有效位元。量測得到的有效位元最高可達到12.55的有效位元，訊號對雜訊及諧波比分別為77.3dB和101.38dB，Schreier品質因數為185.1dB。

關鍵字

連續漸進式 ； 類比至數位轉換器 ； 偵測與迴避切換 ； 同步切換 ； 追蹤切換平均 ； 分離式權重補償 ； 背景平移誤差校正

並列摘要

An analog-to-digital converter (ADC) can convert analog signal in nature to digital signal for digital-signal-processor (DSP). The thesis present a 0.9V 1MS/s 14-bit successive-approximation register (SAR) analog-to-digital converter (ADC) fabricated in 40 nm CMOS.
The design is a sub-ranging SAR ADC architecture. With detect-and-skip (DAS) and align switching method, it can reduce switching energy in capacitor array. Also, tracking average technique can suppress input-referred noise and power consumption of comparator. To solve capacitor mismatch because of small unit capacitor for saving switching power and the restriction of DAS architecture, weight-split compensation overcomes the bottleneck of weight compensation. The proposed background offset mismatch calibration can track the offset mismatch in sub-ranging ADC and adjust capacitor array voltage to solve this problem and save coarse comparator power.
The proposed ADC consumes 8.38μW at a sampling-rate of 1 MS/s. After calibration, DNL and INL are 0.51/-0.54 and 1.34/-1.31 LSB. The measured ENOB can reach 12.55-bit, with SNDR and SFDR are 77.3dB and 101.38dB. FoMS are 185.1 dB.

並列關鍵字

successive-approximation register (SAR) ； analog-to-digital converter (ADC) ； detect-and-skip and aligned switching ； tracking average ； weight-split compensation ； background offset mismatch calibration

參考文獻

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