鍺金氧半電容介面缺陷密度與遲滯現象降低及等效功函數之調變

Interface Trap Density and Hysteresis Reduction of Ge MISCAPs and Effective Work Function Modulation

黃智雄(Chih-Hsiung Huang)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2019年)

https://doi.org/10.6342/NTU201903214

摘要

當電晶體尺寸持續微縮以及效能持續增加，使用高遷移率鍺取代矽做為通道材料以增加驅動電流是重要的發展方向。鍺做為通道材料，最關鍵的問題是形成具有良好介面特性的高品質閘極堆疊。此外，當電晶體尺寸持續微縮，由於氧化層已經無法再微縮，所以必須微縮閘極金屬。為了沉積高深寬比閘極金屬，使用原子層沉積取代物理氣象沉積和化學氣相沉積是重要的發展方向。本篇論文，著重於降低鍺金氧半電容之介面缺陷密度及遲滯現象，以及調變氮化鈦，氮化鋁鈦，氮化鎢和碳氮化鎢在矽/鍺閘極堆疊之等效功函數。
在論文第一部份，探討退火對鋁和鉑電極之鍺閘極堆疊的效應。利用快速熱氧化和原子層沉積形成氧化鋁/氧化鍺/鍺堆疊。鋁電極沉積時，鋁擴散到氧化鍺並形成氧化鍺鋁介面層。而鉑電極元件則能保持氧化層之結構。鋁電極元件(~1011 cm-2eV-1)相較於鉑電極元件(~1012 cm-2eV-1)有較低之介面缺陷密度，驗證氧化鍺鋁相較於氧化鍺，更能有效鈍化鍺表面。沉積鉑之前，先沉積鋁再蝕刻掉，也可以有低介面缺陷密度之電性。介面缺陷密度隨著鋁電極面積增加而降低，表示氧化鍺鋁只在鋁電極下方有效果。氧化鍺鋁在低氧化鍺及低氧化鋁厚度皆可有效鈍化鍺表面。對鋁電極元件，沉積後退火可以更加改善介面缺陷密度和遲滯現象。而金屬後退火，因為有更多鋁擴散到氧化層，所以有最低之介面缺陷密度。但會遲滯現象會比沉積後退火還大，表示過多的鋁在氧化鍺鋁會增加邊緣缺陷密度。對鉑電極電容，沉積後退火可以降低遲滯現象，但無法改善介面缺陷密度。利用混合氫氣體進行金屬後退火可以同時改善介面缺陷密度和遲滯現象，因為氫原子可以有效鈍化閘極堆疊內之缺陷。
在論文第二部分，探討等效功函數之調變，包含p型金屬氮化鈦及n型金屬氮化鋁鈦。利用反應式濺鍍沉積氮化鈦當作三氧化二鋁/氧化鍺/鍺堆疊之金屬。藉由增加氮氣/(氮氣+氬氣)比例，可以調變氮化鈦等效功函數從4.54到4.74 eV。造成等效功函數調變的原因為結晶方向的改變。利用電漿輔助原子層沉積方式沉積氮化鋁鈦當作二氧化矽/矽堆疊之金屬並使用先驅物三乙基鋁提供鋁。在沉積溫度300 oC，以氮化鋁對氮化鈦比例1:4方式沉積氮化鋁鈦，等效功函數可以達到4.61 eV，其中鋁和氧含量分別為21和17 %。在沉積溫度350 oC，氮化鋁鈦之氧含量由17%降至10%，等效功函數可以達到4.55 eV。以氮化鋁對氮化鈦比例1:1方式沉積，可以增加鋁含量至40 %，等效功函數可以達到4.38 eV。
在論文第三部分，探討濺鍍之氮化鎢及電漿輔助原子層沉積之碳氮化鎢等效功函數之調變。利用反應式濺鍍沉積氮化鎢當作二氧化矽/矽堆疊之金屬。藉由改變退火溫度及氮化鎢之氮濃度，可以調變氮化鎢等效功函數從4.29到4.91 eV。等效功函數隨退火溫度增加而增加，隨氮濃度增加而減少。等效功函數調變原因為氮化鎢和二氧化矽介面形成偶極。退火時，氧從二氧化矽擴散至氮化鎢，並在介面形成氮氧化鎢。氮氧化鎢相較於氮化鎢有較大之電負度，因此形成方向由氮氧化鎢到氮化鎢之偶極。增加氮化鎢之氮濃度，可以減緩氧擴散至氮化鎢以減少偶極之形成。利用電漿輔助原子層沉積方式沉積碳氮化鎢當作二氧化矽/矽堆疊之金屬。改變沉積溫度由250至350 oC，可以減少碳氮化鎢之氧含量，並降低等效功函數由4.71至4.46 eV。在沉積溫度350 oC搭配氫氣電漿，可以增加碳氮化鎢之鎢含量並提高等效功函數由4.46至4.74 eV。

關鍵字

鍺 ； 氧化鍺鋁 ； 介面缺陷密度 ； 遲滯現象 ； 沉積後退火 ； 金屬後退火 ； 氮化鈦 ； 氮化鋁鈦 ； 氮化鎢 ； 碳氮化鎢 ； 等效功函數

並列摘要

As the transistor scaling continues and performance requirements increase, using high mobility Ge to replace Si as the channel material to enhance drive current is proposed. For Ge channel material, the most crucial issue is to form high-quality gate stacks with superior interface properties. Besides, as the transistor scaling continues, the gate metal scaling is required due to limited gate oxide thickness scaling. To deposit high aspect ratio gate metal, atomic layer deposition (ALD) is used instead of physical vapor deposition and chemical vapor deposition. In this dissertation, the interface trap density (Dit) and the hysteresis reduction of Ge MISCAPs and the effective work function (EWF) modulation of TiN, TiAlN, WNx, and WNxCy on Si/Ge gate stacks are investigated.
In the first part, the annealing effects on Ge gate stack with Al and Pt electrodes are studied. Rapid thermal oxidation (RTO) and ALD are used to form Al2O3/GeOx/Ge stack. During Al electrode deposition, Al diffuses into GeOx and forms AlGeO interfacial layer. For Pt electrode device, the Al2O¬3/GeOx/Ge stack still maintains intact. The Al electrode device has smaller Dit (~1011 cm-2eV-1) than the Pt electrode device (~1012 cm-2eV-1), indicating well AlGeO passivation as compared to the GeOx. Pt electrode deposition after Al capping/removal process also exhibits low Dit behavior. The increasing Al electrode area decreases Dit, indicating the AlGeO passivation is only effective underneath Al electrode. The AlGeO layer can effectively passivate Ge with scaled GeOx and Al2O3 thickness. For Al electrode device, post deposition annealing can further reduce the Dit and the hysteresis. After post metallization annealing, the lowest Dit is observed due to more Al in the AlGeO layer. However, the hysteresis increases as compared to the post deposition annealing, indicating too much Al in the AlGeO layer increases the slow trap density. For Pt electrode device, post deposition annealing can reduce the hysteresis and no influence on the Dit. After post metallization annealing, both the Dit and the hysteresis can reduce due to atomic hydrogen can passivate the trap in the gate stack.
In the second part, the EWF modulation of p-type metal TiN and n-type metal TiAlN are studied. TiN is deposited on Al2O3/GeOx/Ge stacks by reactive sputtering. By increasing nitrogen gas flow ratio (N2/(N2+Ar)), the EWF of TiN can modulate from 4.54 to 4.74 eV due to crystal orientation variation. TiAlN is deposited on SiO2/Si stacks by plasma-enhanced ALD (PEALD) and the precursor TEA is used to supply Al. At the deposition temperature of 300 oC, the EWF of TiAlN is 4.61 eV with AlN:TiN ratio of 1:4 and the Al content and O content in the TiAlN are 21 and 17 %, respectively. At the deposition temperature of 350 oC, the O content decreases from 17 to 10 % and the EWF can reach 4.55 eV. The Al content increases to 40 % with AlN:TiN ratio of 1:1 and the EWF can reach 4.38 eV.
In the third part, the EWF modulation of sputtered WNx and PEALD WNxCy are studied. WNx is deposited on SiO2/Si stacks by reactive sputtering. By varying annealing temperature and N content in the WNx films, the EWF of WNx can modulate from 4.29 to 4.91 eV. The EWF increases with increasing annealing temperature and decreases with increasing N content. The EWF modulation is due to the dipole formation near the WNx/SiO2 interface. Oxygen diffuses from SiO2 into WNx during annealing and forms the WNxOy near the interface. The dipole with the direction from WNxOy to WNx is formed because the group electronegativity of WNxOy near the WNx/SiO2 interface is larger than that of WNx. The WNx with high N content can mitigate the oxidation and reduce dipole formation. WNxCy is deposited on SiO2/Si stacks by PEALD. The EWF of WNxCy decreases from 4.71 to 4.46 eV with increasing deposition temperature from 250 to 350 oC due to less oxidation of dense WNxCy film. At the deposition temperature of 350 oC and hydrogen plasma, the EWF of WNxCy increases to 4.74 eV due to more W content in the WNxCy film.

並列關鍵字

Ge ； AlGeO ； interface trap density ； hysteresis ； post deposition annealing ； post metallization annealing ； TiN ； TiAlN ； WNx ； WNxCy ； effective work function

參考文獻

Chapter 1

[1] G. E. Moore, “Cramming more components onto integrated circuits),” Proc. IEEE, vol. 86, no. 1, pp. 82–85, Jan. 1998.

[2] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” in IEDM Tech. Dig., Dec. 2003, pp. 978–980.

[3] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” in IEDM Tech. Dig., Dec. 2007, pp. 247–250.

[4] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K. Mistry, “A 22 nm high performance and low-power CMOS technology featuring fully-depleted trigate transistors, self-aligned contacts and high density MIM capacitors,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 131–132.