本篇論文提出了兩個使用台積電90-nm互補式金氧半導體製程於Ka頻段之功率放大器,設計目標是提升電路的線性度、輸出功率、功率附加效率及退縮6-dB處功率附加效率。 於第一個電路中,主要採用了雙重中和技術,功率放大器是使用2.4 V偏壓供電。此差動疊接架構是由四個單級疊接架構與變壓器組合而成,功率放大器在2.4 V以及偏壓0.7 V的情況下,實際量測可得Ka頻段操作小訊號增益14 dB、OP1dB為19.56 dBm以及飽和輸出功率20.24 dBm,於OP1dB點的PAE與PAE的最大值分別為21.45 %與21.9 %,而在P1dB退縮6 dB點的PAE為10.14 %。 第二個電路,主要是以第一顆架構為基礎,並加入線性器及自動調整偏壓等技術來達到提升功率附加效率。此功率放大器在2.4 V以及偏壓0.8 V的情況下,實際量測可得Ka頻段操作小訊號增益14.68 dB、OP1dB為20.15 dBm以及飽和輸出功率20.71 dBm,於OP1dB點的PAE與PAE的最大值分別為25.77 %與25.99%,而在P1dB退縮6 dB點的PAE為15.73 %。與第一顆晶片相比,在相近增益及OP1dB之下,對應之PAE都有明顯的改善。
In this thesis, two Ka-band power amplifier chips implemented in TSMC 90-nm CMOS process are proposed to improve the linearity, output power, PAE and back-off 6-dB efficiency. For the first chip, a Ka-band power amplifier using 2.4 V supply voltage utilizing double neutralization technique is designed and measured. The differential cascode architecture combines four single-stage cascode cells and transformers. With 2.4 V supply voltage and 0.7 V bias voltage, the measured small signal gain is 14 dB, OP1dB is 19.56 dBm, and saturation power is 20.24 dBm. The PAE at OP1dB and peak are 21.45 % and 21.9% respectively. The PAE at 6-dB back-off from P1dB is 10.14 %. The second chip is based on the first one by adding linearizer and adaptive-bias to improve back-off power-added-efficiency. With 2.4 V supply voltage and 0.8 V bias voltage, the measured small signal gain is 14.68 dB, OP1dB is 20.15 dBm, and saturation power is 20.71 dBm. The PAE at OP1dB and peak are 25.77 % and 25.99 % respectively. The PAE at 6-dB back-off from P1dB is 15.73 %. Compared with the first chip, the second chip has similar gain and OP1dB, but PAE at different power levels are all improved.