無摻雜矽/矽鍺異質接面之二維電子氣之材料與電性分析

Material and Electrical Analysis for Two Dimensional Electron Gases in Undoped Si/SiGe Heterostructure

汪子茗(Tz-Ming Wang)

指導教授 ： 李峻霣

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202203328

摘要

隨著摩爾定律持續發展，電晶體的微縮將因為量子穿隧效應而走到極限。對於更快速的計算效能並解決傳統計算機無法解決的難題，量子計算被視為一種解決方式。在所有製作量子點元件的材料中，矽量子點擁有非常長的去相干時間、尺寸微縮能力且與目前大型積體電路的製程相容。藉由在矽金屬氧化物半導體或矽/矽鍺異質結構中的二維電子氣之頂部製作閘極可以實現矽量子點。其中矽/矽鍺異質結構因其介面品質相對矽/氧化物介面來的好，故相形之下更顯優勢。本篇論文將討論無摻雜矽/矽鍺異質結構的長晶、材料分析以及其低溫下的電子傳輸特性。
我們使用超高真空化學氣相沉積來成長四種不同鍺濃度之矽/矽鍺異質結構(包含10, 15, 20與30 %)。針對這些結構進行後續的材料分析包含二次離子質譜儀、X光繞射儀、原子力顯微鏡與蝕刻缺陷密度量測。矽/矽鍺異質結構使用矽烷與鍺烷於550℃下成長，而二次離子質譜儀可以分析漸變式矽鍺層沿著成長方向的元素組成。原子力顯微鏡下可以觀察到矽/矽鍺異質結構因應力釋放而產生的十字網格交叉表面，其表面粗糙度為4.88、10.04、10.72與17.28 nm，數值分別對應鍺濃度為10, 15, 20與30%之矽/矽鍺異質結構。而藉由蝕刻缺陷密度量測實驗，我們發現矽/矽鍺異質結構之蝕刻缺陷密度為2×10^6 cm^(-2)。
為了分析矽/矽鍺異質結構中的電子傳輸特性，我們製作了霍爾元件並放入低溫下進行量測。我們在鍺濃度為15, 20與30 %的元件中觀察到了電流飽和的現象。我們將閘極電壓再次提高後，異質結構內的載子分布由非平衡態轉變回平衡態後，我們發現了負微分電導的情形。此時元件處於低溫下，表面通道產生凍結效應，新注入之電子只能挹入底層二維電子氣通道中，導致電子濃度隨著閘極電壓提升一同升高，並逐漸超越其平衡態的電子濃度。二維電子氣通道內，當新挹入電子速率與電子穿隧出表面的速率相等時，電子濃度將達到飽和。而當表面缺陷被鈍化完畢後，表面通道將開始導通，異質結構內的載子分布也將回歸平衡，導致電子濃度下降。另一方面，電子遷移率在一開始會因為電子屏蔽效應而隨著閘極電壓增加而增加，後續慢慢飽和。接著，電子遷移率會因表層通道開始導通而逐漸下降，最終再一次因雙層通道導通而飽和。鍺濃度為10 %的元件有著與上述相似的直流訊號特性，唯有其電流飽和在一個相對低的數值。可能的原因推測為其矽與矽鍺間的導帶能量差較小，導致其元件導通時電阻過大，也將造成後續霍爾量測時交流訊號的不穩定。根據本論文的數據，我們發現一些與文獻回顧中不同的結論，首先是漸變式矽鍺層從步階式漸變優化成線性漸變並不會提升電子遷移率，而我們也發現電子遷移率與鍺濃度沒有明顯關係。以上這些結論也都將需要更多的實驗與觀察來驗證。

關鍵字

無摻雜矽/矽鍺異質結構二維電子氣 ； 材料分析 ； 霍爾量測

並列摘要

Following Moore’s Law, the scaling of transistors will not be able to continue due to quantum tunneling effects. In addition, for future high-performance computing and some intractable problems which cannot be solved by conventional computers, quantum computing is considered one of the most powerful technology. Among all solid-state platforms, Si quantum dots have advantages of long decoherence, scalability, and compatibility with VLSI technology. Si quantum dots can be realized by top gating a two-dimensional electron gas (2DEG) in a Si metal-oxide-semiconductor (MOS) or a Si/SiGe heterostructure. The latter structure is promising due to its much better interface quality than the Si/oxide interface. In this thesis, the epitaxial growth and material characterization of undoped Si/SiGe heterostructures, and the electron transport properties at cryogenic temperatures are presented.
The epitaxial growth of Si/SiGe heterostructures with four Ge fractions (10, 15, 20, and 30 %) was performed by ultra-high vacuum chemical vapor deposition (UHVCVD). The heterostructures were characterized by secondary ion mass spectroscopy (SIMS), X-ray diffractometer (XRD), atomic force microscopy (AFM) and etch pit density (EPD) measurements. Si/SiGe heterostructures were grown at 550℃ using precursors of silane and germane. Elementary analysis along the growth direction by SIMS provides the information of the graded SiGe buffer layers. AFM figures show cross-hatched surfaces for the strain relaxation. The surface roughness of four Si/SiGe heterostructures with Ge fractions of 10 %, 15 %, 20 %, and 30 % are 4.88, 10.04, 10.72, and 17.28 nm, respectively. A low number of 2×10^6 cm^(-2) is achieved by EPD experiment.
To characterize electron transport properties in the Si/SiGe heterostructures, Hall bar devices were fabricated and low-temperature measurements were performed. For the DC characteristics of the devices with Ge fractions of 15, 20, and 30 %, there is current saturation observed. Negative differential trans-conductance is then observed at higher gate biases due to a crossover of carrier distributions in the heterostructures from non-equilibrium to equilibrium. At cryogenic temperatures, the surface channels freeze out and the injected electrons can only accumulate in the buried 2DEG channel. It leads to an increasing density with the gate voltage and the density surpasses the equilibrium density. The density saturates as the electron tunneling rate is equal to the injection rates into the buried channel. With the surface defects fully passivated, the surface channel starts to conduct and the heterostructure will be back to equilibrium, leading to a density drop. On the other hand, the electron mobility increases with gate voltage in the beginning due to stronger electron screening effect, and then saturates. The mobility then decreases once the surface channel conducts, and finally saturates again in the end, which is the effective mobility under parallel conduction contributed by both surface and buried 2DEG channels. Devices with a Ge fraction of 10% show a similar trend for DC characteristics, except for its saturation current at a relatively low level. This might be due to the small conduction band offset between Si and SiGe, leading to a large device resistance and unstable AC signals for Hall measurements. Note that in contrast to prior work, the optimization for SiGe graded buffer layer from stepped-graded to linearly-graded seems not helpful for the mobility improvement. Moreover, there is no clear relationship between the Ge fraction and mobility, either, and further investigation is required.

並列關鍵字

undoped Si/SiGe heterostructure 2DEG ； material analysis ； Hall measurement

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