This thesis reports a 2D analytical simulation for the capacitance characteristics of partially-depleted (PD) silicon on insulator (SOI) NMOS devices. In chapter 2, we make a brief description of the mechanism for kink effect of PD SOI NMOS devices and study the triggering VDS with the conditions in different operating temperature and different thin film dopping concentration. In chapter 3, by using the 2D device simulator(Medici), we make a simulation of CDG,CSG,CGD,CGS versus VDS for different gate voltages. For the simulation results, we discuss and present some physical viewpoints.