The thesis reports DC analysis of PD SOI NMOS device considering back gate bias effect. Due to the buried oxide structure, the back gate bias effect of the PD SOI CMOS devices may be quite different from the devices with no back-gate bias. Chapter 1 gives a brief introduction about SOI CMOS devices and the scaling trends, including the comparison of the difference between the PD SOI and the FD SOI CMOS devices. Chapter 2 describes current conduction mechanism and equivalent circuit of the PD SOI NMOS device in saturation region considering the positive back gate bias effect. Chapter 3 discusses some relative effect of the PD SOI NMOS device in saturation region considering the back gate bias effect. Chapter 4 is conclusion and future work.