考慮高介電係數閘極介電層之100奈米絕緣體上矽金氧半元件之電容分析

Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics

林育生(Yu-Sheng Lin)

指導教授 ： 郭正邦

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.02377

摘要

本論文中提出了100奈米絕緣體上矽金氧半元件的本體和邊緣電容分析。
第二章說明不同氧化層厚度下，本體電容和邊緣電容彼此之間的關係。
第三章研究高介電係數材料作為閘極介電層時的本體電容及邊緣電容彼此的關係，以相同實際厚度或等效厚度為前提下，與傳統的氧化層作比較。
第四章探討閘極穿隧漏電流對元件電容特性的影響，以相同實際厚度或等效厚度為前提下，討論不同閘極介電層的穿隧現象。
第五章探討二維的元件物理特性，討論不同閘極介電層、邊牆材料、和汲極偏壓下，次臨界區域的邊緣引發位障下降現象。

關鍵字

絕緣體上矽 ； 高介電係數 ； 電容

並列摘要

This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices.
In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses.
In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide.
In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics.
Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages.

並列關鍵字

SOI ； high k ； capacitance

參考文獻

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[1.5] J. P. Colinge, “Thin-Film SOI Technology: The Solution to Many Submicron CMOS Problems, “ IEDM Dig., p.817, 1989.

[1.8] E. Leobandung, et al., “Scalability of SOI Technology into 0.13 μm 1.2V CMOS Generation, “IEEE Tech. Dig. Int. Electron Devices Meet., p. 403, 1998.

[1.11] H.–S. P. Wong, “Beyond the conventional transistor,” IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.