60-GHz 緩衝放大器與低相位變異可變增益放大器之研製

Design of 60-GHz Buffer Amplifier and Low Phase Variation Variable Gain Amplifier

謝家瑜(Chia-Yu Hsieh)

指導教授 ： 林坤佑

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01321

摘要

隨著通訊技術和晶片研製技術的演進，無線傳輸、高速傳輸成為發展的趨勢，而由於60 GHz頻段是用於無線個人區域網路(WPAN)的免授權頻段，具備安全、有效率之短距傳輸功能，因而成為發展的重心。在晶片製程上，金氧半場效電晶體(CMOS)製程由於高整合性、低成本、低功率的優點，逐漸取代其他製程成為各種類比積體電路積極發展的方向。
在本論文中，設計並實現了兩種不同用途的放大器，分別為緩衝放大器以及可變增益放大器，兩者均是利用金氧半場效電晶體(CMOS)製程實現且應用於60 GHz頻段。
第一部分設計並實現60 GHz頻段的緩衝放大器，在系統中可以有效的將前級電路的信號放大至發射器前端的功率放大器，使功率放大器不會因為前級先飽和而不能達到最大的輸出功率。此放大器是使用65 nm CMOS製程製作，使用薄膜微帶線(Thin-film microstrip lines, TFMS lines)進行匹配。此電路的量測結果與模擬結果有良好的一致性，在消耗有限功率下，可以達到高增益、高輸出功率的特性；並且因為使用寬頻的匹配技巧，使得小信號和大信號都具有寬頻的表現。此緩衝放大器在14 GHz的3-dB 頻寬下，可以達到23.7 dB的最大增益，以及10.3 dBm的最大輸出功率(Psat)、16%的最大的峰值PAE，因此也可作為中等功率放大器。
第二部分設計並實現60 GHz頻段的可變增益放大器，此電路可以用於接收器前端的相位陣列系統。此放大器是使用90 nm CMOS的製程製作，採用電流控制架構(current steering)達到控制增益的效果，並使用薄膜微帶線進行匹配。此電路的特性除了小信號增益平坦、增益控制範圍大之外，還增加了相位補償的設計，使此電路在調整增益同時，輸出信號的相位變化僅在6.6°以內。低相位變異的可變增益放大器用於相位陣列系統時，可降低操作的複雜度；若應用於向量疊加調變器則可增加調變信號的品質。

關鍵字

無線個人區域網路(WPAN) ； 金氧半場效電晶體 ； 功率放大器 ； 可變增益放大器 ； 相位陣列系統 ； 向量疊加調變器

並列摘要

According to the progress of communication techniques and process technologies, wireless communication and high data-rate transmissions become the trend of developments. Recently, 60 GHz becomes a more important developed frequency band, since it is an unlicensed band for application of WPAN, which can provide the secure and efficient short-distant transmission. On the other hand, in process technologies, because of the advantages of high integration potential, low cost and low power in CMOS, it gradually replaces other process to become a major process to realize analog circuits.
In this thesis, two amplifiers, which are buffer amplifier and variable gain amplifier (VGA), are applied in 60 GHz and realized by CMOS technology
The 60 GHz buffer amplifier, which can amplify signal from prior stage to input of front-end power amplifier and guarantee the maximum output power can be delivered without saturation at prior stages, is discussed in first part. This amplifier is implemented by 65-nm CMOS process, and matched by TFMS lines. With reasonable power consumption, the amplifier achieves high gain and high output power with broadband characteristics of both small-signal and large-signal due to broadband matching technique. This buffer amplifier can achieve maximum linear-gain of 23.7 dB with 3-dB bandwidth of 14 GHz with maximum saturated output power of 10.3 dBm and maximum peak PAE of 16%. Therefore, it also can be applied as a medium power amplifier.
In the second part, the 60 GHz VGA, which can be applied in receiver phase array systems, is designed and fabricated. With current-steering topology to realize variable gain, this VGA is implemented by 90-nm CMOS process, and matched TFMS lines. In addition to the characteristics of high linear-gain with good flatness and large gain variation range, the technique to compensate insertion phase is implemented in this VGA. As a result, the insertion phase variation is lower than 6.6° versus gain tuning. Low phase variation VGA can be applied in phase array systems to reduce the complexity of control systems while can enhance the quality of modulated signals in vector sum modulators.

並列關鍵字

Wireless personal area network (WLAN) ； CMOS ； power amplifier ； variable gain amplifier ； phase array system ； vector sum modulator

參考文獻

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