毫米波低相位變異可變増益放大器與低雜訊放大器之研製

Research on Millimeter-Wave Low-phase-variation Variable-gain Amplifier and Low-noise Amplifier

盧德任(De-Ren Lu)

指導教授 ： 林坤佑

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.01154

摘要

隨著通訊技術和晶片研製技術的演進，毫米波頻帶快速的發展。這是由於毫米波頻帶在無線傳輸應用上擁有較大的頻寬且高速傳輸。在本論文中，兩種不同用途的放大器，分別為低雜訊放大器以及可變增益放大器，兩者均利用金氧半場效電晶體(CMOS)製程實現，前者應用於W頻段，而後者應用於V頻段。
第一部分設計並實現W頻段的低雜訊放大器且此放大器是使用65 nm CMOS製程製作。在接收端中低雜訊放大器為一個重要的元件。此電路採用四級疊接的架構達到高增益和寬頻的效果。此低雜訊放大器在117.5 GHz有25.3 dB的最高增益和在75.5-120.5 GHz頻帶中，此放大器有大於20 dB。此電路在87-100 GHz範圍內有6-8.3 dB的量測雜訊指數，-3 dBm的1-dB壓縮點的輸出功率(OP1dB)，以及0.5 dBm的飽和輸出功率。此低雜訊放大器在2-V的電源供應下靜態電流為24 mA。
第二部分設計並實現60 GHz頻段的可變增益放大器，此電路可以用於接收器前端的相位陣列系統。此放大器是使用65 nm CMOS的製程製作，採用兩級的電流控制架構(current steering)達到控制增益的效果。共振技巧除了可用來消除寄生電容外，還可以在可變增益放大器在增益變化時，降低相位變化。除此之外，這個方法同時可以降低可變增益放大器的雜訊指數。此電路在54-62 GHz的1-dB頻寬下，有18 dB的最高增益。另外，此電路有4.4 dB的最低雜訊指數。當增益從15.5 dB至0.5 dB變化時，輸出信號的相位變化在6.2°以內。在1.8-V的電源供應下，全部的DC功耗為18 mW。低相位變異的可變增益放大器用於相位陣列系統時，可降低操作的複雜度；若應用於向量疊加調變器則可增加調變信號的品質。

關鍵字

低雜訊放大器 ； 可變增益放大器 ； V頻段 ； 60-GHz ； W頻段 ； 電流控制架構 ； 相位陣列系統

並列摘要

As the progress of communication techniques and the advance in process technology, the interest in the millimeter-wave band has rapidly grown since the wide bandwidth allows high data transferring rate for short-range wireless applications. In this thesis, a low noise amplifier (LNA) and a variable-gain amplifier (VGA) are implemented in CMOS technology for W-band and V-band, respectively.
In the first part, the W-band LNA, which is an essential component in the receiver, has been designed by TSMC 65-nm 1P9M CMOS process. The circuit is implemented by 4-stage cascode configuration to achieve high gain and wideband performance. This LNA has a peak gain of 25.3 dB at 117.5 GHz, and the gain is better than 20 dB from 75.5 GHz to 120.5 GHz. It features the measured noise figure is from 6 to 8.3 dB from 87 to 100 GHz, OP1dB of -3 dBm, and Psat of 0.5 dBm. The quiescent current of the LNA is 24 mA from 2-V supply voltage.
In the second part, the V-band VGA can be applied in the receiver of a phased-array system. The circuit has been implemented by TSMC 65-nm 1P9M CMOS process and adopted two current-steering stages to achieve variable-gain function. Resonant technique is proposed to cancel the intrinsic capacitor and reduce insertion phase variation while the gain of the VGA is varied. In addition, the noise figure of the VGA can be reduced by using this method simultaneously. A peak gain of 18 dB with a 1-dB bandwidth of 54-62 GHz is measured. In addition, the circuit has a minimum measured NF of 4.4 dB. The insertion phase variation is lower than 6.2° while the gain is varied from 15 dB to 0 dB. The total dc power consumption is 18 mW from 1.8-V supply voltage. A low-phase-variation VGA can not only reduce the complexity of control systems in the phased-array system but also enhance the quality of modulated signals in vector sum modulators.

並列關鍵字

LNA ； VGA ； CMOS ； V-band ； 60-GHz ； W-band ； current-steering ； phased-array system

參考文獻

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