應用於微波頻段之低雜訊放大器及相移器之研究

Investigation of Low Noise Amplifier and Phase Shifter for Microwave Applications

曾暐哲(Wei-Je Tseng)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.00606

摘要

在本論文中開發了一個變質高電子移動率電晶體(mHEMT)的低雜訊放大器(LNA)，以及三個互補金氧半導體(CMOS)的相移器，分別用於天文接收機與相位陣列系統。
在ALMA(Atacama 大型毫米波及次毫米波陣列)天文接收機的低溫彈夾中，4-12 GHz的低雜訊放大器是一個重要的基礎元件，原因在於低雜訊放大器的等效雜訊溫度會影響接收訊號的敏感度進而主宰接收機的性能。為達到嚴峻的低雜訊要求以及低製作成本的考量，我們採用高參雜銦(indium)通道的mHEMT來實現此低雜訊放大器。此低雜訊放大器晶片的量測結果，在室溫下有29±1 dB的功率增益及1.9 dB的最小雜訊因素，在直流功率消耗為160 mW情況下。封裝後將直流功率消耗降至 20 mW，在室溫下仍可有25±2 dB的功率增益及1.9 dB的最小雜訊因素。當溫度降至22.4 K，量測結果顯示此放大器有25±2 dB的功率增益及15.1 K的最小等效雜訊溫度。
CMOS相位陣列系統於現代通訊系統是未來的趨勢，原因在於CMOS可整合RF前端與基頻元件而減少製程上的成本，而相位陣列系統的空間多樣性與高陣列增益可增加系統的頻譜效率。然而，要建構此種系統相移器的性能則為首要考量。於此篇論文中，將介紹三種不同架構的CMOS相移器。
首先，要呈現的是一個微小化三位元切換式相移器。藉由縮減電感的大小，晶片面積可減少至0.285 mm2。此電路實現在0.18-μm CMOS製程上。此電路於21-29 GHz展示了小於5.3° 的均方根(RMS)相位誤差以及小於1.3 dB 的均方根(RMS)增益誤差。於24 GHz，平均的插入損耗與反射損耗分別為11 dB與7 dB。
接著，一個基於注入鎖定振盪器的相移器設計與製造於0.18-μm CMOS製程上，且晶片面積為0.22 mm2且直流消耗為14 mW。低品質因素設計的LC槽以及寬調整範圍設計的振盪器，當輸入功率為-3 dBm時可延展注入鎖定範圍至38%，同時也可降低注入源的相位雜訊在可調相位範圍內的衰減。這些特性可提高基於注入鎖定振盪器的相移器，於相位陣列系統中的可行性與可靠度。
最後，一個新的向量加法相移器架構設計與製造於0.13-μm CMOS製程上。藉由降低供給偏壓與減少放大器的數量，直流消耗可減少至20 mW。較少的聯結器與平衡轉換器可減少面積至0.45 mm2。此電路於17-24 GHz展示了1.5-10° 的均方根(RMS)相位誤差以及1.2-1.6 dB 的均方根(RMS)增益誤差。

關鍵字

低溫低雜訊放大器 ； 相移器

並列摘要

In this dissertation, a mHEMT low noise amplifier (LNA) and three CMOS phase shifters are developed for radio astronomy receiver and phased-array system, respectively.
A 4-12 GHz LNA is an important building block at cold cartridge of ALMA (Atacama Large Millimeter/Sub-millimeter Array) radio astronomy receiver. Since the equivalent noise temperature of LNA affects the sensitivity of the received signal and dominates the performance of the receiver. In order to achieve the stringent noise requirement, the metamorphic HEMT technology employed to realize the LNA. It takes the advantages of low cost GaAs process and highly doped indium channel to achieve low noise performance. The on-chip measurements at room temperature with 160 mW dc consumption for LNA give a power gain of 29±1 dB and a minimum noise figure of 1.9 dB. After packaging, at room temperature the LNA with 20 mW dc consumption gives a power gain of 25±2 dB and a minimum noise figure of 1.9 dB. When cooled down to 22.4 K the LNA with 20 mW dc consumption shows a power gain of 25±2 dB and a minimum equivalent noise temperature of 15.1 K.
CMOS phased-array system is a future trend in modern communication system, since the CMOS technology reduce the fabrication cost by integrating both the RF front-end and baseband circuit in a single chip, and the special diversity and high array gain of phased-array system can increase the spectral efficiency of the system. However, to establish such system the performance of the phase shifter must be considered primarily. In this thesis, three different topologies of CMOS phase shifters will be introduced.
First of all, a miniature 3-bit switching phase shifter is presented. By shrinking the size of inductors, the size can be reduced to 0.285 mm2. The circuit is implemented with 0.18-μm CMOS technology. The circuit demonstrates RMS phase error less than 5.3° and RMS gain error less than 1.3 dB from 21-29 GHz. The average insertion loss and return loss at 24 GHz are 11 and 7 dB, respectively.
Further, a phase shifter based on the injection locked oscillator is designed and fabricated in a 0.18-μm CMOS technology, which has only 0.22 mm2 chip area and 14-mW power dissipation. Low quality factor design of the LC tank and wide tuning range design of free-running oscillator can extend the locking range up to 38% with -3 dBm input power and also reduces phase noise degradation of the locked oscillator in the phase tuning range. These features can enhance the feasibility and reliability of the injection locked oscillator based phase shifter in phased-array system.
Finally, a new architecture of vector sum phase shifter is designed and fabricated in a 0.13-μm CMOS technology. By lowering down supply voltage and reducing the number of amplifiers, the power dissipation can be reduced to 20 mW. Fewer passive components such as couplers and baluns can shrink the chip size to 0.45 mm2. The measured results demonstrate RMS phase errors of 1.5-10° and RMS gain errors of 1.2-1.6 dB from 17-24 GHz.

並列關鍵字

Cryogenic low noise amplifier ； phase shifter

參考文獻

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