本論文設計的主題為應用於Ku頻帶智慧型天線系統上的相移器與功率放大器的積體電路設計。 本論文使用WIN所提供的0.15 um PHEMT製程來實現了12GHz二位元與三位元的開關型相移器設計,其中擁有90°輸出相位差電路的兩位元開關型相移器在12 GHz的表現上,最大的插入損耗值為6.3dB,均方根相位誤差值為2.099度,均方根增益誤差值則為0.382 dB,其晶片整體面積為1.5 mm2,而三位元的開關型相移器則另外加入了45°相位差的電路,在12GHz的最大插入損耗值表現上為7.9 dB,均方根相位誤差值為1.62度,均方根增益誤差值則為0.308 dB,其晶片整體面積為1.5 mm2,在此次兩個相移器的晶片設計上,其量測值與初始的模擬值十分接近。 本論文另外使用了TSMC所提供的0.18 um CMOS製程實現了一個12 GHz全積體化功率放大器設計,此次放大器設計晶片其12GHz小訊號增益值為16.9 dB且晶片整體面積為0.81511 × 0.575 mm2,輸出功率與輸出1 dB壓縮點的值分別為15.27 dBm與11.26 dBm,而功率增加效率則為15.3%。
The design of the Ku-band phase shifter and power amplifier for phase array system applications are presented in this thesis. A 2-bit and a 3-bit phase shifter MMIC using switch-type topology are designed and fabricated on WIN 0.15 μm pHEMT process. The 2-bit switch-type phase shifter MMIC with 90° phase resolution achieves a maximum insertion loss of 6.3 dB at 12 GHz. The RMS phase error of the 2-bit phase shifter is 2.099 degree and the RMS gain error is 0.382 dB. The chip size is 1.5 mm2 including all testing pads. Another 3-bit switch-type phase shifter MMIC with 45° phase resolution achieves a maximum insertion loss of 7.9 dB at 12 GHz. The RMS phase error of the 3-bit phase shifter is 1.62 degree and the RMS gain error is 0.308 dB. The chip size is 1.5 mm2. The simulated and measured results have good agreement for the presented MMICs. A 12 GHz fully-integrated power amplifier is designed and fabricated on TSMC 0.18 μm CMOS technology. The CMOS power amplifier MMIC achieves a small signal gain of 16.9 dB at 12 GHz with chip size 0.81511 × 0.575 mm2. The output power and output 1 dB compression point is 15.27 dBm and 11.26 dBm, respectively. The power added efficiency is 15.3 %.